3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_common.h>
32 #include <asm/arch/clocks.h>
33 #include <asm/omap_gpio.h>
36 struct prcm_regs const **prcm =
37 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
38 struct dplls const **dplls_data =
39 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
40 struct vcores_data const **omap_vcores =
41 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
43 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
44 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
46 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
50 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
53 static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
54 {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
55 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
56 {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
57 {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
58 {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
59 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
60 {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
63 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
64 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
65 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
66 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
67 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
68 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
69 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
70 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
73 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
74 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
75 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
76 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
77 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
78 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
79 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
80 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
83 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
84 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
85 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
86 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
87 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
88 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
90 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
93 static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
94 {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
95 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
96 {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
97 {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
98 {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
99 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
100 {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
103 static const struct dpll_params
104 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
105 {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
106 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
107 {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
108 {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
109 {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
110 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
111 {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
114 static const struct dpll_params
115 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
116 {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
117 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
118 {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
119 {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
120 {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
121 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
122 {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
125 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
126 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
127 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
128 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
129 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
130 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
131 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
132 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
135 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
136 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
138 {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
139 {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
140 {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
142 {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
145 /* ABE M & N values with sys_clk as source */
146 static const struct dpll_params
147 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
148 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
149 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
150 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
151 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
152 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
154 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
157 /* ABE M & N values with 32K clock as source */
158 static const struct dpll_params abe_dpll_params_32k_196608khz = {
159 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
162 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
163 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
164 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
165 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
166 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
167 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
168 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
169 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
172 struct dplls omap5_dplls_es1 = {
173 .mpu = mpu_dpll_params_800mhz,
174 .core = core_dpll_params_2128mhz_ddr532,
175 .per = per_dpll_params_768mhz,
176 .iva = iva_dpll_params_2330mhz,
177 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
178 .abe = abe_dpll_params_sysclk_196608khz,
180 .abe = &abe_dpll_params_32k_196608khz,
182 .usb = usb_dpll_params_1920mhz
185 struct pmic_data palmas = {
186 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
187 .step = 10000, /* 10 mV represented in uV */
189 * Offset codes 1-6 all give the base voltage in Palmas
190 * Offset code 0 switches OFF the SMPS
195 struct vcores_data omap5430_volts = {
196 .mpu.value = VDD_MPU,
197 .mpu.addr = SMPS_REG_ADDR_12_MPU,
200 .core.value = VDD_CORE,
201 .core.addr = SMPS_REG_ADDR_8_CORE,
202 .core.pmic = &palmas,
205 .mm.addr = SMPS_REG_ADDR_45_IVA,
209 struct vcores_data omap5432_volts = {
210 .mpu.value = VDD_MPU_5432,
211 .mpu.addr = SMPS_REG_ADDR_12_MPU,
214 .core.value = VDD_CORE_5432,
215 .core.addr = SMPS_REG_ADDR_8_CORE,
216 .core.pmic = &palmas,
218 .mm.value = VDD_MM_5432,
219 .mm.addr = SMPS_REG_ADDR_45_IVA,
224 * Enable essential clock domains, modules and
225 * do some additional special settings needed
227 void enable_basic_clocks(void)
229 u32 const clk_domains_essential[] = {
230 (*prcm)->cm_l4per_clkstctrl,
231 (*prcm)->cm_l3init_clkstctrl,
232 (*prcm)->cm_memif_clkstctrl,
233 (*prcm)->cm_l4cfg_clkstctrl,
237 u32 const clk_modules_hw_auto_essential[] = {
238 (*prcm)->cm_l3_2_gpmc_clkctrl,
239 (*prcm)->cm_memif_emif_1_clkctrl,
240 (*prcm)->cm_memif_emif_2_clkctrl,
241 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
242 (*prcm)->cm_wkup_gpio1_clkctrl,
243 (*prcm)->cm_l4per_gpio2_clkctrl,
244 (*prcm)->cm_l4per_gpio3_clkctrl,
245 (*prcm)->cm_l4per_gpio4_clkctrl,
246 (*prcm)->cm_l4per_gpio5_clkctrl,
247 (*prcm)->cm_l4per_gpio6_clkctrl,
251 u32 const clk_modules_explicit_en_essential[] = {
252 (*prcm)->cm_wkup_gptimer1_clkctrl,
253 (*prcm)->cm_l3init_hsmmc1_clkctrl,
254 (*prcm)->cm_l3init_hsmmc2_clkctrl,
255 (*prcm)->cm_l4per_gptimer2_clkctrl,
256 (*prcm)->cm_wkup_wdtimer2_clkctrl,
257 (*prcm)->cm_l4per_uart3_clkctrl,
258 (*prcm)->cm_l4per_i2c1_clkctrl,
262 /* Enable optional additional functional clock for GPIO4 */
263 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
264 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
266 /* Enable 96 MHz clock for MMC1 & MMC2 */
267 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
268 HSMMC_CLKCTRL_CLKSEL_MASK);
269 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
270 HSMMC_CLKCTRL_CLKSEL_MASK);
272 /* Set the correct clock dividers for mmc */
273 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
274 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
275 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
276 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
278 /* Select 32KHz clock as the source of GPTIMER1 */
279 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
280 GPTIMER1_CLKCTRL_CLKSEL_MASK);
282 do_enable_clocks(clk_domains_essential,
283 clk_modules_hw_auto_essential,
284 clk_modules_explicit_en_essential,
287 /* Select 384Mhz for GPU as its the POR for ES1.0 */
288 setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
289 CLKSEL_GPU_HYD_GCLK_MASK);
290 setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
291 CLKSEL_GPU_CORE_GCLK_MASK);
293 /* Enable SCRM OPT clocks for PER and CORE dpll */
294 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
295 OPTFCLKEN_SCRM_PER_MASK);
296 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
297 OPTFCLKEN_SCRM_CORE_MASK);
300 void enable_basic_uboot_clocks(void)
302 u32 const clk_domains_essential[] = {
306 u32 const clk_modules_hw_auto_essential[] = {
310 u32 const clk_modules_explicit_en_essential[] = {
311 (*prcm)->cm_l4per_mcspi1_clkctrl,
312 (*prcm)->cm_l4per_i2c2_clkctrl,
313 (*prcm)->cm_l4per_i2c3_clkctrl,
314 (*prcm)->cm_l4per_i2c4_clkctrl,
315 (*prcm)->cm_l3init_hsusbtll_clkctrl,
316 (*prcm)->cm_l3init_hsusbhost_clkctrl,
317 (*prcm)->cm_l3init_fsusb_clkctrl,
321 do_enable_clocks(clk_domains_essential,
322 clk_modules_hw_auto_essential,
323 clk_modules_explicit_en_essential,
328 * Enable non-essential clock domains, modules and
329 * do some additional special settings needed
331 void enable_non_essential_clocks(void)
333 u32 const clk_domains_non_essential[] = {
334 (*prcm)->cm_mpu_m3_clkstctrl,
335 (*prcm)->cm_ivahd_clkstctrl,
336 (*prcm)->cm_dsp_clkstctrl,
337 (*prcm)->cm_dss_clkstctrl,
338 (*prcm)->cm_sgx_clkstctrl,
339 (*prcm)->cm1_abe_clkstctrl,
340 (*prcm)->cm_c2c_clkstctrl,
341 (*prcm)->cm_cam_clkstctrl,
342 (*prcm)->cm_dss_clkstctrl,
343 (*prcm)->cm_sdma_clkstctrl,
347 u32 const clk_modules_hw_auto_non_essential[] = {
348 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
349 (*prcm)->cm_ivahd_ivahd_clkctrl,
350 (*prcm)->cm_ivahd_sl2_clkctrl,
351 (*prcm)->cm_dsp_dsp_clkctrl,
352 (*prcm)->cm_l3instr_l3_3_clkctrl,
353 (*prcm)->cm_l3instr_l3_instr_clkctrl,
354 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
355 (*prcm)->cm_l3init_hsi_clkctrl,
356 (*prcm)->cm_l4per_hdq1w_clkctrl,
360 u32 const clk_modules_explicit_en_non_essential[] = {
361 (*prcm)->cm1_abe_aess_clkctrl,
362 (*prcm)->cm1_abe_pdm_clkctrl,
363 (*prcm)->cm1_abe_dmic_clkctrl,
364 (*prcm)->cm1_abe_mcasp_clkctrl,
365 (*prcm)->cm1_abe_mcbsp1_clkctrl,
366 (*prcm)->cm1_abe_mcbsp2_clkctrl,
367 (*prcm)->cm1_abe_mcbsp3_clkctrl,
368 (*prcm)->cm1_abe_slimbus_clkctrl,
369 (*prcm)->cm1_abe_timer5_clkctrl,
370 (*prcm)->cm1_abe_timer6_clkctrl,
371 (*prcm)->cm1_abe_timer7_clkctrl,
372 (*prcm)->cm1_abe_timer8_clkctrl,
373 (*prcm)->cm1_abe_wdt3_clkctrl,
374 (*prcm)->cm_l4per_gptimer9_clkctrl,
375 (*prcm)->cm_l4per_gptimer10_clkctrl,
376 (*prcm)->cm_l4per_gptimer11_clkctrl,
377 (*prcm)->cm_l4per_gptimer3_clkctrl,
378 (*prcm)->cm_l4per_gptimer4_clkctrl,
379 (*prcm)->cm_l4per_mcspi2_clkctrl,
380 (*prcm)->cm_l4per_mcspi3_clkctrl,
381 (*prcm)->cm_l4per_mcspi4_clkctrl,
382 (*prcm)->cm_l4per_mmcsd3_clkctrl,
383 (*prcm)->cm_l4per_mmcsd4_clkctrl,
384 (*prcm)->cm_l4per_mmcsd5_clkctrl,
385 (*prcm)->cm_l4per_uart1_clkctrl,
386 (*prcm)->cm_l4per_uart2_clkctrl,
387 (*prcm)->cm_l4per_uart4_clkctrl,
388 (*prcm)->cm_wkup_keyboard_clkctrl,
389 (*prcm)->cm_wkup_wdtimer2_clkctrl,
390 (*prcm)->cm_cam_iss_clkctrl,
391 (*prcm)->cm_cam_fdif_clkctrl,
392 (*prcm)->cm_dss_dss_clkctrl,
393 (*prcm)->cm_sgx_sgx_clkctrl,
397 /* Enable optional functional clock for ISS */
398 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
400 /* Enable all optional functional clocks of DSS */
401 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
403 do_enable_clocks(clk_domains_non_essential,
404 clk_modules_hw_auto_non_essential,
405 clk_modules_explicit_en_non_essential,
408 /* Put camera module in no sleep mode */
409 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
410 MODULE_CLKCTRL_MODULEMODE_MASK,
411 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
412 MODULE_CLKCTRL_MODULEMODE_SHIFT);
415 void hw_data_init(void)
417 u32 omap_rev = omap_revision();
422 *prcm = &omap5_es1_prcm;
423 *dplls_data = &omap5_dplls_es1;
424 *omap_vcores = &omap5430_volts;
428 *prcm = &omap5_es1_prcm;
429 *dplls_data = &omap5_dplls_es1;
430 *omap_vcores = &omap5432_volts;
434 printf("\n INVALID OMAP REVISION ");