3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_common.h>
32 #include <asm/arch/clocks.h>
35 struct prcm_regs const **prcm =
36 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
37 struct dplls const **dplls_data =
38 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
40 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
41 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
42 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
43 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
44 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
45 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
46 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
47 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
51 {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
52 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
53 {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
54 {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
55 {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
57 {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
60 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
61 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
62 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
63 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
64 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
65 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
66 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
67 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
70 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
71 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
72 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
73 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
74 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
75 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
76 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
77 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
80 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
81 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
83 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
84 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
85 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
86 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
87 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
90 static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
91 {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
92 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
93 {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
94 {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
95 {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
96 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97 {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
100 static const struct dpll_params
101 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
102 {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
103 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
104 {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
105 {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
106 {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
107 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
108 {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
111 static const struct dpll_params
112 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
113 {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
114 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
115 {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
116 {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
117 {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
118 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
119 {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
122 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
123 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
124 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
125 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
126 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
127 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
128 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
129 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
132 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
133 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
134 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
135 {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
136 {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
137 {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
138 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
139 {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
142 /* ABE M & N values with sys_clk as source */
143 static const struct dpll_params
144 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
145 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
146 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
147 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
148 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
149 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
150 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
151 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
154 /* ABE M & N values with 32K clock as source */
155 static const struct dpll_params abe_dpll_params_32k_196608khz = {
156 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
159 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
160 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
161 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
162 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
163 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
164 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
165 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
166 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
169 struct dplls omap5_dplls_es1 = {
170 .mpu = mpu_dpll_params_800mhz,
171 .core = core_dpll_params_2128mhz_ddr532,
172 .per = per_dpll_params_768mhz,
173 .iva = iva_dpll_params_2330mhz,
174 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
175 .abe = abe_dpll_params_sysclk_196608khz,
177 .abe = &abe_dpll_params_32k_196608khz,
179 .usb = usb_dpll_params_1920mhz
183 * Enable essential clock domains, modules and
184 * do some additional special settings needed
186 void enable_basic_clocks(void)
188 u32 const clk_domains_essential[] = {
189 (*prcm)->cm_l4per_clkstctrl,
190 (*prcm)->cm_l3init_clkstctrl,
191 (*prcm)->cm_memif_clkstctrl,
192 (*prcm)->cm_l4cfg_clkstctrl,
196 u32 const clk_modules_hw_auto_essential[] = {
197 (*prcm)->cm_l3_2_gpmc_clkctrl,
198 (*prcm)->cm_memif_emif_1_clkctrl,
199 (*prcm)->cm_memif_emif_2_clkctrl,
200 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
201 (*prcm)->cm_wkup_gpio1_clkctrl,
202 (*prcm)->cm_l4per_gpio2_clkctrl,
203 (*prcm)->cm_l4per_gpio3_clkctrl,
204 (*prcm)->cm_l4per_gpio4_clkctrl,
205 (*prcm)->cm_l4per_gpio5_clkctrl,
206 (*prcm)->cm_l4per_gpio6_clkctrl,
210 u32 const clk_modules_explicit_en_essential[] = {
211 (*prcm)->cm_wkup_gptimer1_clkctrl,
212 (*prcm)->cm_l3init_hsmmc1_clkctrl,
213 (*prcm)->cm_l3init_hsmmc2_clkctrl,
214 (*prcm)->cm_l4per_gptimer2_clkctrl,
215 (*prcm)->cm_wkup_wdtimer2_clkctrl,
216 (*prcm)->cm_l4per_uart3_clkctrl,
217 (*prcm)->cm_l4per_i2c1_clkctrl,
221 /* Enable optional additional functional clock for GPIO4 */
222 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
223 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
225 /* Enable 96 MHz clock for MMC1 & MMC2 */
226 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
227 HSMMC_CLKCTRL_CLKSEL_MASK);
228 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
229 HSMMC_CLKCTRL_CLKSEL_MASK);
231 /* Set the correct clock dividers for mmc */
232 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
233 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
234 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
235 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
237 /* Select 32KHz clock as the source of GPTIMER1 */
238 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
239 GPTIMER1_CLKCTRL_CLKSEL_MASK);
241 do_enable_clocks(clk_domains_essential,
242 clk_modules_hw_auto_essential,
243 clk_modules_explicit_en_essential,
246 /* Select 384Mhz for GPU as its the POR for ES1.0 */
247 setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
248 CLKSEL_GPU_HYD_GCLK_MASK);
249 setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
250 CLKSEL_GPU_CORE_GCLK_MASK);
252 /* Enable SCRM OPT clocks for PER and CORE dpll */
253 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
254 OPTFCLKEN_SCRM_PER_MASK);
255 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
256 OPTFCLKEN_SCRM_CORE_MASK);
259 void enable_basic_uboot_clocks(void)
261 u32 const clk_domains_essential[] = {
265 u32 const clk_modules_hw_auto_essential[] = {
269 u32 const clk_modules_explicit_en_essential[] = {
270 (*prcm)->cm_l4per_mcspi1_clkctrl,
271 (*prcm)->cm_l4per_i2c2_clkctrl,
272 (*prcm)->cm_l4per_i2c3_clkctrl,
273 (*prcm)->cm_l4per_i2c4_clkctrl,
274 (*prcm)->cm_l3init_hsusbtll_clkctrl,
275 (*prcm)->cm_l3init_hsusbhost_clkctrl,
276 (*prcm)->cm_l3init_fsusb_clkctrl,
280 do_enable_clocks(clk_domains_essential,
281 clk_modules_hw_auto_essential,
282 clk_modules_explicit_en_essential,
287 * Enable non-essential clock domains, modules and
288 * do some additional special settings needed
290 void enable_non_essential_clocks(void)
292 u32 const clk_domains_non_essential[] = {
293 (*prcm)->cm_mpu_m3_clkstctrl,
294 (*prcm)->cm_ivahd_clkstctrl,
295 (*prcm)->cm_dsp_clkstctrl,
296 (*prcm)->cm_dss_clkstctrl,
297 (*prcm)->cm_sgx_clkstctrl,
298 (*prcm)->cm1_abe_clkstctrl,
299 (*prcm)->cm_c2c_clkstctrl,
300 (*prcm)->cm_cam_clkstctrl,
301 (*prcm)->cm_dss_clkstctrl,
302 (*prcm)->cm_sdma_clkstctrl,
306 u32 const clk_modules_hw_auto_non_essential[] = {
307 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
308 (*prcm)->cm_ivahd_ivahd_clkctrl,
309 (*prcm)->cm_ivahd_sl2_clkctrl,
310 (*prcm)->cm_dsp_dsp_clkctrl,
311 (*prcm)->cm_l3instr_l3_3_clkctrl,
312 (*prcm)->cm_l3instr_l3_instr_clkctrl,
313 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
314 (*prcm)->cm_l3init_hsi_clkctrl,
315 (*prcm)->cm_l4per_hdq1w_clkctrl,
319 u32 const clk_modules_explicit_en_non_essential[] = {
320 (*prcm)->cm1_abe_aess_clkctrl,
321 (*prcm)->cm1_abe_pdm_clkctrl,
322 (*prcm)->cm1_abe_dmic_clkctrl,
323 (*prcm)->cm1_abe_mcasp_clkctrl,
324 (*prcm)->cm1_abe_mcbsp1_clkctrl,
325 (*prcm)->cm1_abe_mcbsp2_clkctrl,
326 (*prcm)->cm1_abe_mcbsp3_clkctrl,
327 (*prcm)->cm1_abe_slimbus_clkctrl,
328 (*prcm)->cm1_abe_timer5_clkctrl,
329 (*prcm)->cm1_abe_timer6_clkctrl,
330 (*prcm)->cm1_abe_timer7_clkctrl,
331 (*prcm)->cm1_abe_timer8_clkctrl,
332 (*prcm)->cm1_abe_wdt3_clkctrl,
333 (*prcm)->cm_l4per_gptimer9_clkctrl,
334 (*prcm)->cm_l4per_gptimer10_clkctrl,
335 (*prcm)->cm_l4per_gptimer11_clkctrl,
336 (*prcm)->cm_l4per_gptimer3_clkctrl,
337 (*prcm)->cm_l4per_gptimer4_clkctrl,
338 (*prcm)->cm_l4per_mcspi2_clkctrl,
339 (*prcm)->cm_l4per_mcspi3_clkctrl,
340 (*prcm)->cm_l4per_mcspi4_clkctrl,
341 (*prcm)->cm_l4per_mmcsd3_clkctrl,
342 (*prcm)->cm_l4per_mmcsd4_clkctrl,
343 (*prcm)->cm_l4per_mmcsd5_clkctrl,
344 (*prcm)->cm_l4per_uart1_clkctrl,
345 (*prcm)->cm_l4per_uart2_clkctrl,
346 (*prcm)->cm_l4per_uart4_clkctrl,
347 (*prcm)->cm_wkup_keyboard_clkctrl,
348 (*prcm)->cm_wkup_wdtimer2_clkctrl,
349 (*prcm)->cm_cam_iss_clkctrl,
350 (*prcm)->cm_cam_fdif_clkctrl,
351 (*prcm)->cm_dss_dss_clkctrl,
352 (*prcm)->cm_sgx_sgx_clkctrl,
356 /* Enable optional functional clock for ISS */
357 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
359 /* Enable all optional functional clocks of DSS */
360 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
362 do_enable_clocks(clk_domains_non_essential,
363 clk_modules_hw_auto_non_essential,
364 clk_modules_explicit_en_non_essential,
367 /* Put camera module in no sleep mode */
368 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
369 MODULE_CLKCTRL_MODULEMODE_MASK,
370 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
371 MODULE_CLKCTRL_MODULEMODE_SHIFT);
374 void hw_data_init(void)
376 u32 omap_rev = omap_revision();
381 *prcm = &omap5_es1_prcm;
382 *dplls_data = &omap5_dplls_es1;
386 *prcm = &omap5_es1_prcm;
387 *dplls_data = &omap5_dplls_es1;
391 printf("\n INVALID OMAP REVISION ");