3 * Functions for omap5 based boards.
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 * Sricharan <r.sricharan@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/armv7.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/clock.h>
20 #include <linux/sizes.h>
21 #include <asm/utils.h>
22 #include <asm/arch/gpio.h>
24 #include <asm/omap_common.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
30 static struct gpio_bank gpio_bank_54xx[8] = {
31 { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
32 { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
33 { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
34 { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
35 { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
36 { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
37 { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
38 { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
41 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
43 void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
46 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
48 for (i = 0; i < size; i++, pad++)
49 writel(pad->val, base + pad->offset);
52 #ifdef CONFIG_SPL_BUILD
53 /* LPDDR2 specific IO settings */
54 static void io_settings_lpddr2(void)
56 const struct ctrl_ioregs *ioregs;
59 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
60 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
61 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
62 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
63 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
64 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
65 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
66 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
67 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
70 /* DDR3 specific IO settings */
71 static void io_settings_ddr3(void)
74 const struct ctrl_ioregs *ioregs;
77 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
78 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
79 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
81 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
82 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
83 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
85 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
86 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
89 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
90 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
93 /* omap5432 does not use lpddr2 */
94 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
96 writel(ioregs->ctrl_emif_sdram_config_ext,
97 (*ctrl)->control_emif1_sdram_config_ext);
99 writel(ioregs->ctrl_emif_sdram_config_ext,
100 (*ctrl)->control_emif2_sdram_config_ext);
103 /* Disable DLL select */
104 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
107 (*ctrl)->control_port_emif1_sdram_config);
109 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
112 (*ctrl)->control_port_emif2_sdram_config);
114 writel(ioregs->ctrl_ddr_ctrl_ext_0,
115 (*ctrl)->control_ddr_control_ext_0);
120 * Some tuning of IOs for optimal power and performance
122 void do_io_settings(void)
124 u32 io_settings = 0, mask = 0;
125 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
127 /* Impedance settings EMMC, C2C 1,2, hsi2 */
128 mask = (ds_mask << 2) | (ds_mask << 8) |
129 (ds_mask << 16) | (ds_mask << 18);
130 io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
132 io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
133 (ds_45_ohm << 18) | (ds_60_ohm << 2);
134 writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
136 /* Impedance settings Mcspi2 */
137 mask = (ds_mask << 30);
138 io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
140 io_settings |= (ds_60_ohm << 30);
141 writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
143 /* Impedance settings C2C 3,4 */
144 mask = (ds_mask << 14) | (ds_mask << 16);
145 io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
147 io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
148 writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
150 /* Slew rate settings EMMC, C2C 1,2 */
151 mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
152 io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
154 io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
155 writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
157 /* Slew rate settings hsi2, Mcspi2 */
158 mask = (sc_mask << 24) | (sc_mask << 28);
159 io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
161 io_settings |= (sc_fast << 28) | (sc_fast << 24);
162 writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
164 /* Slew rate settings C2C 3,4 */
165 mask = (sc_mask << 16) | (sc_mask << 18);
166 io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
168 io_settings |= (sc_na << 16) | (sc_na << 18);
169 writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
171 /* impedance and slew rate settings for usb */
172 mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
173 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
174 io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
176 io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
177 (ds_60_ohm << 23) | (sc_fast << 20) |
178 (sc_fast << 17) | (sc_fast << 14);
179 writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
181 if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
182 io_settings_lpddr2();
187 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
188 {0x45, 0x1}, /* 12 MHz */
189 {-1, -1}, /* 13 MHz */
190 {0x63, 0x2}, /* 16.8 MHz */
191 {0x57, 0x2}, /* 19.2 MHz */
192 {0x20, 0x1}, /* 26 MHz */
193 {-1, -1}, /* 27 MHz */
194 {0x41, 0x3} /* 38.4 MHz */
197 void srcomp_enable(void)
199 u32 srcomp_value, mul_factor, div_factor, clk_val, i;
200 u32 sysclk_ind = get_sys_clk_index();
201 u32 omap_rev = omap_revision();
206 mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
207 div_factor = srcomp_parameters[sysclk_ind].divide_factor;
209 for (i = 0; i < 4; i++) {
210 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
212 ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
213 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
214 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
215 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
218 if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
219 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
220 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
221 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
223 for (i = 0; i < 4; i++) {
225 readl((*ctrl)->control_srcomp_north_side + i*4);
226 srcomp_value &= ~PWRDWN_XS_MASK;
228 (*ctrl)->control_srcomp_north_side + i*4);
230 while (((readl((*ctrl)->control_srcomp_north_side + i*4)
231 & SRCODE_READ_XS_MASK) >>
232 SRCODE_READ_XS_SHIFT) == 0)
236 readl((*ctrl)->control_srcomp_north_side + i*4);
237 srcomp_value &= ~OVERRIDE_XS_MASK;
239 (*ctrl)->control_srcomp_north_side + i*4);
242 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
243 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
244 DIVIDE_FACTOR_XS_MASK);
245 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
246 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
247 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
249 for (i = 0; i < 4; i++) {
251 readl((*ctrl)->control_srcomp_north_side + i*4);
252 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
254 (*ctrl)->control_srcomp_north_side + i*4);
257 readl((*ctrl)->control_srcomp_north_side + i*4);
258 srcomp_value &= ~OVERRIDE_XS_MASK;
260 (*ctrl)->control_srcomp_north_side + i*4);
264 readl((*ctrl)->control_srcomp_east_side_wkup);
265 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
266 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
269 readl((*ctrl)->control_srcomp_east_side_wkup);
270 srcomp_value &= ~OVERRIDE_XS_MASK;
271 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
273 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
274 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
275 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
277 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
278 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
279 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
281 for (i = 0; i < 4; i++) {
282 while (((readl((*ctrl)->control_srcomp_north_side + i*4)
283 & SRCODE_READ_XS_MASK) >>
284 SRCODE_READ_XS_SHIFT) == 0)
288 readl((*ctrl)->control_srcomp_north_side + i*4);
289 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
291 (*ctrl)->control_srcomp_north_side + i*4);
294 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
295 SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
299 readl((*ctrl)->control_srcomp_east_side_wkup);
300 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
301 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
306 void config_data_eye_leveling_samples(u32 emif_base)
308 const struct ctrl_ioregs *ioregs;
312 /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
313 if (emif_base == EMIF1_BASE)
314 writel(ioregs->ctrl_emif_sdram_config_ext_final,
315 (*ctrl)->control_emif1_sdram_config_ext);
316 else if (emif_base == EMIF2_BASE)
317 writel(ioregs->ctrl_emif_sdram_config_ext_final,
318 (*ctrl)->control_emif2_sdram_config_ext);
321 void init_cpu_configuration(void)
325 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
327 * L2ACTLR: Ensure to enable the following:
328 * 3: Disable clean/evict push to external
329 * 4: Disable WriteUnique and WriteLineUnique transactions from master
330 * 8: Disable DVM/CMO message broadcast
333 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
336 void init_omap_revision(void)
339 * For some of the ES2/ES1 boards ID_CODE is not reliable:
340 * Also, ES1 and ES2 have different ARM revisions
341 * So use ARM revision for identification
343 unsigned int rev = cortex_rev();
345 switch (readl(CONTROL_ID_CODE)) {
346 case OMAP5430_CONTROL_ID_CODE_ES1_0:
347 *omap_si_rev = OMAP5430_ES1_0;
348 if (rev == MIDR_CORTEX_A15_R2P2)
349 *omap_si_rev = OMAP5430_ES2_0;
351 case OMAP5432_CONTROL_ID_CODE_ES1_0:
352 *omap_si_rev = OMAP5432_ES1_0;
353 if (rev == MIDR_CORTEX_A15_R2P2)
354 *omap_si_rev = OMAP5432_ES2_0;
356 case OMAP5430_CONTROL_ID_CODE_ES2_0:
357 *omap_si_rev = OMAP5430_ES2_0;
359 case OMAP5432_CONTROL_ID_CODE_ES2_0:
360 *omap_si_rev = OMAP5432_ES2_0;
362 case DRA752_CONTROL_ID_CODE_ES1_0:
363 *omap_si_rev = DRA752_ES1_0;
365 case DRA752_CONTROL_ID_CODE_ES1_1:
366 *omap_si_rev = DRA752_ES1_1;
368 case DRA722_CONTROL_ID_CODE_ES1_0:
369 *omap_si_rev = DRA722_ES1_0;
372 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
374 init_cpu_configuration();
377 void reset_cpu(ulong ignored)
379 u32 omap_rev = omap_revision();
382 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
383 * So use cold reset in case instead.
385 if (omap_rev == OMAP5430_ES1_0)
386 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
388 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
393 return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
396 void setup_warmreset_time(void)
398 u32 rst_time, rst_val;
400 #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
401 rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
403 rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
405 rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
407 if (rst_time > RSTTIME1_MASK)
408 rst_time = RSTTIME1_MASK;
410 rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
412 writel(rst_val, (*prcm)->prm_rsttime);
415 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
416 u32 cpu_rev_comb, u32 cpu_variant,
419 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
422 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
423 u32 cpu_variant, u32 cpu_rev)
425 omap_smc1(OMAP5_SERVICE_ACR_SET, acr);