2 * Copyright (C) 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Heungjun Kim <riverful.kim@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/clock.h>
28 #include <asm/arch/clk.h>
34 #ifndef CONFIG_SYS_CLK_FREQ_C100
35 #define CONFIG_SYS_CLK_FREQ_C100 12000000
37 #ifndef CONFIG_SYS_CLK_FREQ_C110
38 #define CONFIG_SYS_CLK_FREQ_C110 24000000
41 /* s5pc110: return pll clock frequency */
42 static unsigned long s5pc100_get_pll_clk(int pllreg)
44 struct s5pc100_clock *clk =
45 (struct s5pc100_clock *)samsung_get_base_clock();
46 unsigned long r, m, p, s, mask, fout;
51 r = readl(&clk->apll_con);
54 r = readl(&clk->mpll_con);
57 r = readl(&clk->epll_con);
60 r = readl(&clk->hpll_con);
63 printf("Unsupported PLL (%d)\n", pllreg);
68 * APLL_CON: MIDV [25:16]
69 * MPLL_CON: MIDV [23:16]
70 * EPLL_CON: MIDV [23:16]
71 * HPLL_CON: MIDV [23:16]
85 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
86 freq = CONFIG_SYS_CLK_FREQ_C100;
87 fout = m * (freq / (p * (1 << s)));
92 /* s5pc100: return pll clock frequency */
93 static unsigned long s5pc110_get_pll_clk(int pllreg)
95 struct s5pc110_clock *clk =
96 (struct s5pc110_clock *)samsung_get_base_clock();
97 unsigned long r, m, p, s, mask, fout;
102 r = readl(&clk->apll_con);
105 r = readl(&clk->mpll_con);
108 r = readl(&clk->epll_con);
111 r = readl(&clk->vpll_con);
114 printf("Unsupported PLL (%d)\n", pllreg);
119 * APLL_CON: MIDV [25:16]
120 * MPLL_CON: MIDV [25:16]
121 * EPLL_CON: MIDV [24:16]
122 * VPLL_CON: MIDV [24:16]
124 if (pllreg == APLL || pllreg == MPLL)
129 m = (r >> 16) & mask;
136 freq = CONFIG_SYS_CLK_FREQ_C110;
137 if (pllreg == APLL) {
140 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
141 fout = m * (freq / (p * (1 << (s - 1))));
143 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
144 fout = m * (freq / (p * (1 << s)));
149 /* s5pc110: return ARM clock frequency */
150 static unsigned long s5pc110_get_arm_clk(void)
152 struct s5pc110_clock *clk =
153 (struct s5pc110_clock *)samsung_get_base_clock();
155 unsigned long dout_apll, armclk;
156 unsigned int apll_ratio;
158 div = readl(&clk->div0);
160 /* APLL_RATIO: [2:0] */
161 apll_ratio = div & 0x7;
163 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
169 /* s5pc100: return ARM clock frequency */
170 static unsigned long s5pc100_get_arm_clk(void)
172 struct s5pc100_clock *clk =
173 (struct s5pc100_clock *)samsung_get_base_clock();
175 unsigned long dout_apll, armclk;
176 unsigned int apll_ratio, arm_ratio;
178 div = readl(&clk->div0);
180 /* ARM_RATIO: [6:4] */
181 arm_ratio = (div >> 4) & 0x7;
182 /* APLL_RATIO: [0] */
183 apll_ratio = div & 0x1;
185 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
186 armclk = dout_apll / (arm_ratio + 1);
191 /* s5pc100: return HCLKD0 frequency */
192 static unsigned long get_hclk(void)
194 struct s5pc100_clock *clk =
195 (struct s5pc100_clock *)samsung_get_base_clock();
196 unsigned long hclkd0;
197 uint div, d0_bus_ratio;
199 div = readl(&clk->div0);
200 /* D0_BUS_RATIO: [10:8] */
201 d0_bus_ratio = (div >> 8) & 0x7;
203 hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
208 /* s5pc100: return PCLKD1 frequency */
209 static unsigned long get_pclkd1(void)
211 struct s5pc100_clock *clk =
212 (struct s5pc100_clock *)samsung_get_base_clock();
213 unsigned long d1_bus, pclkd1;
214 uint div, d1_bus_ratio, pclkd1_ratio;
216 div = readl(&clk->div0);
217 /* D1_BUS_RATIO: [14:12] */
218 d1_bus_ratio = (div >> 12) & 0x7;
219 /* PCLKD1_RATIO: [18:16] */
220 pclkd1_ratio = (div >> 16) & 0x7;
223 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
224 pclkd1 = d1_bus / (pclkd1_ratio + 1);
229 /* s5pc110: return HCLKs frequency */
230 static unsigned long get_hclk_sys(int dom)
232 struct s5pc110_clock *clk =
233 (struct s5pc110_clock *)samsung_get_base_clock();
237 unsigned int hclk_sys_ratio;
242 div = readl(&clk->div0);
245 * HCLK_MSYS_RATIO: [10:8]
246 * HCLK_DSYS_RATIO: [19:16]
247 * HCLK_PSYS_RATIO: [27:24]
249 offset = 8 + (dom << 0x3);
251 hclk_sys_ratio = (div >> offset) & 0xf;
253 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
258 /* s5pc110: return PCLKs frequency */
259 static unsigned long get_pclk_sys(int dom)
261 struct s5pc110_clock *clk =
262 (struct s5pc110_clock *)samsung_get_base_clock();
266 unsigned int pclk_sys_ratio;
268 div = readl(&clk->div0);
271 * PCLK_MSYS_RATIO: [14:12]
272 * PCLK_DSYS_RATIO: [22:20]
273 * PCLK_PSYS_RATIO: [30:28]
275 offset = 12 + (dom << 0x3);
277 pclk_sys_ratio = (div >> offset) & 0x7;
279 pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
284 /* s5pc110: return peripheral clock frequency */
285 static unsigned long s5pc110_get_pclk(void)
287 return get_pclk_sys(CLK_P);
290 /* s5pc100: return peripheral clock frequency */
291 static unsigned long s5pc100_get_pclk(void)
296 /* s5pc1xx: return uart clock frequency */
297 static unsigned long s5pc1xx_get_uart_clk(int dev_index)
299 if (cpu_is_s5pc110())
300 return s5pc110_get_pclk();
302 return s5pc100_get_pclk();
305 /* s5pc1xx: return pwm clock frequency */
306 static unsigned long s5pc1xx_get_pwm_clk(void)
308 if (cpu_is_s5pc110())
309 return s5pc110_get_pclk();
311 return s5pc100_get_pclk();
314 unsigned long get_pll_clk(int pllreg)
316 if (cpu_is_s5pc110())
317 return s5pc110_get_pll_clk(pllreg);
319 return s5pc100_get_pll_clk(pllreg);
322 unsigned long get_arm_clk(void)
324 if (cpu_is_s5pc110())
325 return s5pc110_get_arm_clk();
327 return s5pc100_get_arm_clk();
330 unsigned long get_pwm_clk(void)
332 return s5pc1xx_get_pwm_clk();
335 unsigned long get_uart_clk(int dev_index)
337 return s5pc1xx_get_uart_clk(dev_index);
340 void set_mmc_clk(int dev_index, unsigned int div)