2 * Copyright (C) 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Heungjun Kim <riverful.kim@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/clock.h>
28 #include <asm/arch/clk.h>
34 #ifndef CONFIG_SYS_CLK_FREQ_C100
35 #define CONFIG_SYS_CLK_FREQ_C100 12000000
37 #ifndef CONFIG_SYS_CLK_FREQ_C110
38 #define CONFIG_SYS_CLK_FREQ_C110 24000000
41 unsigned long (*get_pclk)(void);
42 unsigned long (*get_arm_clk)(void);
43 unsigned long (*get_pll_clk)(int);
45 /* s5pc110: return pll clock frequency */
46 static unsigned long s5pc100_get_pll_clk(int pllreg)
48 struct s5pc100_clock *clk =
49 (struct s5pc100_clock *)samsung_get_base_clock();
50 unsigned long r, m, p, s, mask, fout;
55 r = readl(&clk->apll_con);
58 r = readl(&clk->mpll_con);
61 r = readl(&clk->epll_con);
64 r = readl(&clk->hpll_con);
67 printf("Unsupported PLL (%d)\n", pllreg);
72 * APLL_CON: MIDV [25:16]
73 * MPLL_CON: MIDV [23:16]
74 * EPLL_CON: MIDV [23:16]
75 * HPLL_CON: MIDV [23:16]
89 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
90 freq = CONFIG_SYS_CLK_FREQ_C100;
91 fout = m * (freq / (p * (1 << s)));
96 /* s5pc100: return pll clock frequency */
97 static unsigned long s5pc110_get_pll_clk(int pllreg)
99 struct s5pc110_clock *clk =
100 (struct s5pc110_clock *)samsung_get_base_clock();
101 unsigned long r, m, p, s, mask, fout;
106 r = readl(&clk->apll_con);
109 r = readl(&clk->mpll_con);
112 r = readl(&clk->epll_con);
115 r = readl(&clk->vpll_con);
118 printf("Unsupported PLL (%d)\n", pllreg);
123 * APLL_CON: MIDV [25:16]
124 * MPLL_CON: MIDV [25:16]
125 * EPLL_CON: MIDV [24:16]
126 * VPLL_CON: MIDV [24:16]
128 if (pllreg == APLL || pllreg == MPLL)
133 m = (r >> 16) & mask;
140 freq = CONFIG_SYS_CLK_FREQ_C110;
141 if (pllreg == APLL) {
144 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
145 fout = m * (freq / (p * (1 << (s - 1))));
147 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
148 fout = m * (freq / (p * (1 << s)));
153 /* s5pc110: return ARM clock frequency */
154 static unsigned long s5pc110_get_arm_clk(void)
156 struct s5pc110_clock *clk =
157 (struct s5pc110_clock *)samsung_get_base_clock();
159 unsigned long dout_apll, armclk;
160 unsigned int apll_ratio;
162 div = readl(&clk->div0);
164 /* APLL_RATIO: [2:0] */
165 apll_ratio = div & 0x7;
167 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
173 /* s5pc100: return ARM clock frequency */
174 static unsigned long s5pc100_get_arm_clk(void)
176 struct s5pc100_clock *clk =
177 (struct s5pc100_clock *)samsung_get_base_clock();
179 unsigned long dout_apll, armclk;
180 unsigned int apll_ratio, arm_ratio;
182 div = readl(&clk->div0);
184 /* ARM_RATIO: [6:4] */
185 arm_ratio = (div >> 4) & 0x7;
186 /* APLL_RATIO: [0] */
187 apll_ratio = div & 0x1;
189 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
190 armclk = dout_apll / (arm_ratio + 1);
195 /* s5pc100: return HCLKD0 frequency */
196 static unsigned long get_hclk(void)
198 struct s5pc100_clock *clk =
199 (struct s5pc100_clock *)samsung_get_base_clock();
200 unsigned long hclkd0;
201 uint div, d0_bus_ratio;
203 div = readl(&clk->div0);
204 /* D0_BUS_RATIO: [10:8] */
205 d0_bus_ratio = (div >> 8) & 0x7;
207 hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
212 /* s5pc100: return PCLKD1 frequency */
213 static unsigned long get_pclkd1(void)
215 struct s5pc100_clock *clk =
216 (struct s5pc100_clock *)samsung_get_base_clock();
217 unsigned long d1_bus, pclkd1;
218 uint div, d1_bus_ratio, pclkd1_ratio;
220 div = readl(&clk->div0);
221 /* D1_BUS_RATIO: [14:12] */
222 d1_bus_ratio = (div >> 12) & 0x7;
223 /* PCLKD1_RATIO: [18:16] */
224 pclkd1_ratio = (div >> 16) & 0x7;
227 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
228 pclkd1 = d1_bus / (pclkd1_ratio + 1);
233 /* s5pc110: return HCLKs frequency */
234 static unsigned long get_hclk_sys(int dom)
236 struct s5pc110_clock *clk =
237 (struct s5pc110_clock *)samsung_get_base_clock();
241 unsigned int hclk_sys_ratio;
246 div = readl(&clk->div0);
249 * HCLK_MSYS_RATIO: [10:8]
250 * HCLK_DSYS_RATIO: [19:16]
251 * HCLK_PSYS_RATIO: [27:24]
253 offset = 8 + (dom << 0x3);
255 hclk_sys_ratio = (div >> offset) & 0xf;
257 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
262 /* s5pc110: return PCLKs frequency */
263 static unsigned long get_pclk_sys(int dom)
265 struct s5pc110_clock *clk =
266 (struct s5pc110_clock *)samsung_get_base_clock();
270 unsigned int pclk_sys_ratio;
272 div = readl(&clk->div0);
275 * PCLK_MSYS_RATIO: [14:12]
276 * PCLK_DSYS_RATIO: [22:20]
277 * PCLK_PSYS_RATIO: [30:28]
279 offset = 12 + (dom << 0x3);
281 pclk_sys_ratio = (div >> offset) & 0x7;
283 pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
288 /* s5pc110: return peripheral clock frequency */
289 static unsigned long s5pc110_get_pclk(void)
291 return get_pclk_sys(CLK_P);
294 /* s5pc100: return peripheral clock frequency */
295 static unsigned long s5pc100_get_pclk(void)
300 void s5p_clock_init(void)
302 if (cpu_is_s5pc110()) {
303 get_pll_clk = s5pc110_get_pll_clk;
304 get_arm_clk = s5pc110_get_arm_clk;
305 get_pclk = s5pc110_get_pclk;
307 get_pll_clk = s5pc100_get_pll_clk;
308 get_arm_clk = s5pc100_get_arm_clk;
309 get_pclk = s5pc100_get_pclk;