git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/socfpga/clock_manager.c

   1 /*
   2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clock_manager.h>
  10
  11 DECLARE_GLOBAL_DATA_PTR;
  12
  13 static const struct socfpga_clock_manager *clock_manager_base =
  14         (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  15
  16 static void cm_wait_for_lock(uint32_t mask)
  17 {
  18         register uint32_t inter_val;
  19         do {
  20                 inter_val = readl(&clock_manager_base->inter) & mask;
  21         } while (inter_val != mask);
  22 }
  23
  24 /* function to poll in the fsm busy bit */
  25 static void cm_wait_for_fsm(void)
  26 {
  27         while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
  28                 ;
  29 }
  30
  31 /*
  32  * function to write the bypass register which requires a poll of the
  33  * busy bit
  34  */
  35 static void cm_write_bypass(uint32_t val)
  36 {
  37         writel(val, &clock_manager_base->bypass);
  38         cm_wait_for_fsm();
  39 }
  40
  41 /* function to write the ctrl register which requires a poll of the busy bit */
  42 static void cm_write_ctrl(uint32_t val)
  43 {
  44         writel(val, &clock_manager_base->ctrl);
  45         cm_wait_for_fsm();
  46 }
  47
  48 /* function to write a clock register that has phase information */
  49 static void cm_write_with_phase(uint32_t value,
  50                                 uint32_t reg_address, uint32_t mask)
  51 {
  52         /* poll until phase is zero */
  53         while (readl(reg_address) & mask)
  54                 ;
  55
  56         writel(value, reg_address);
  57
  58         while (readl(reg_address) & mask)
  59                 ;
  60 }
  61
  62 /*
  63  * Setup clocks while making no assumptions about previous state of the clocks.
  64  *
  65  * Start by being paranoid and gate all sw managed clocks
  66  * Put all plls in bypass
  67  * Put all plls VCO registers back to reset value (bandgap power down).
  68  * Put peripheral and main pll src to reset value to avoid glitch.
  69  * Delay 5 us.
  70  * Deassert bandgap power down and set numerator and denominator
  71  * Start 7 us timer.
  72  * set internal dividers
  73  * Wait for 7 us timer.
  74  * Enable plls
  75  * Set external dividers while plls are locking
  76  * Wait for pll lock
  77  * Assert/deassert outreset all.
  78  * Take all pll's out of bypass
  79  * Clear safe mode
  80  * set source main and peripheral clocks
  81  * Ungate clocks
  82  */
  83
  84 void cm_basic_init(const cm_config_t *cfg)
  85 {
  86         uint32_t start, timeout;
  87
  88         /* Start by being paranoid and gate all sw managed clocks */
  89
  90         /*
  91          * We need to disable nandclk
  92          * and then do another apb access before disabling
  93          * gatting off the rest of the periperal clocks.
  94          */
  95         writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
  96                 readl(&clock_manager_base->per_pll.en),
  97                 &clock_manager_base->per_pll.en);
  98
  99         /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
 100         writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
 101                 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
 102                 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
 103                 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
 104                 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
 105                 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
 106                 &clock_manager_base->main_pll.en);
 107
 108         writel(0, &clock_manager_base->sdr_pll.en);
 109
 110         /* now we can gate off the rest of the peripheral clocks */
 111         writel(0, &clock_manager_base->per_pll.en);
 112
 113         /* Put all plls in bypass */
 114         cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
 115                         CLKMGR_BYPASS_MAINPLL);
 116
 117         /*
 118          * Put all plls VCO registers back to reset value.
 119          * Some code might have messed with them.
 120          */
 121         writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
 122                &clock_manager_base->main_pll.vco);
 123         writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
 124                &clock_manager_base->per_pll.vco);
 125         writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
 126                &clock_manager_base->sdr_pll.vco);
 127
 128         /*
 129          * The clocks to the flash devices and the L4_MAIN clocks can
 130          * glitch when coming out of safe mode if their source values
 131          * are different from their reset value.  So the trick it to
 132          * put them back to their reset state, and change input
 133          * after exiting safe mode but before ungating the clocks.
 134          */
 135         writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
 136                &clock_manager_base->per_pll.src);
 137         writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
 138                &clock_manager_base->main_pll.l4src);
 139
 140         /* read back for the required 5 us delay. */
 141         readl(&clock_manager_base->main_pll.vco);
 142         readl(&clock_manager_base->per_pll.vco);
 143         readl(&clock_manager_base->sdr_pll.vco);
 144
 145
 146         /*
 147          * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 148          * with numerator and denominator.
 149          */
 150         writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
 151                &clock_manager_base->main_pll.vco);
 152
 153         writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
 154                &clock_manager_base->per_pll.vco);
 155
 156         writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
 157                &clock_manager_base->sdr_pll.vco);
 158
 159         /*
 160          * Time starts here
 161          * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
 162          */
 163         start = get_timer(0);
 164         /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
 165         timeout = 7;
 166
 167         /* main mpu */
 168         writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
 169
 170         /* main main clock */
 171         writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
 172
 173         /* main for dbg */
 174         writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
 175
 176         /* main for cfgs2fuser0clk */
 177         writel(cfg->cfg2fuser0clk,
 178                &clock_manager_base->main_pll.cfgs2fuser0clk);
 179
 180         /* Peri emac0 50 MHz default to RMII */
 181         writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
 182
 183         /* Peri emac1 50 MHz default to RMII */
 184         writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
 185
 186         /* Peri QSPI */
 187         writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
 188
 189         writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
 190
 191         /* Peri pernandsdmmcclk */
 192         writel(cfg->pernandsdmmcclk,
 193                &clock_manager_base->per_pll.pernandsdmmcclk);
 194
 195         /* Peri perbaseclk */
 196         writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
 197
 198         /* Peri s2fuser1clk */
 199         writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
 200
 201         /* 7 us must have elapsed before we can enable the VCO */
 202         while (get_timer(start) < timeout)
 203                 ;
 204
 205         /* Enable vco */
 206         /* main pll vco */
 207         writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 208                &clock_manager_base->main_pll.vco);
 209
 210         /* periferal pll */
 211         writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 212                &clock_manager_base->per_pll.vco);
 213
 214         /* sdram pll vco */
 215         writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 216                &clock_manager_base->sdr_pll.vco);
 217
 218         /* L3 MP and L3 SP */
 219         writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
 220
 221         writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
 222
 223         writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
 224
 225         /* L4 MP, L4 SP, can0, and can1 */
 226         writel(cfg->perdiv, &clock_manager_base->per_pll.div);
 227
 228         writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
 229
 230 #define LOCKED_MASK \
 231         (CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
 232         CLKMGR_INTER_PERPLLLOCKED_MASK  | \
 233         CLKMGR_INTER_MAINPLLLOCKED_MASK)
 234
 235         cm_wait_for_lock(LOCKED_MASK);
 236
 237         /* write the sdram clock counters before toggling outreset all */
 238         writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
 239                &clock_manager_base->sdr_pll.ddrdqsclk);
 240
 241         writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
 242                &clock_manager_base->sdr_pll.ddr2xdqsclk);
 243
 244         writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
 245                &clock_manager_base->sdr_pll.ddrdqclk);
 246
 247         writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
 248                &clock_manager_base->sdr_pll.s2fuser2clk);
 249
 250         /*
 251          * after locking, but before taking out of bypass
 252          * assert/deassert outresetall
 253          */
 254         uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
 255
 256         /* assert main outresetall */
 257         writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 258                &clock_manager_base->main_pll.vco);
 259
 260         uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
 261
 262         /* assert pheriph outresetall */
 263         writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 264                &clock_manager_base->per_pll.vco);
 265
 266         /* assert sdram outresetall */
 267         writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
 268                 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
 269                 &clock_manager_base->sdr_pll.vco);
 270
 271         /* deassert main outresetall */
 272         writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 273                &clock_manager_base->main_pll.vco);
 274
 275         /* deassert pheriph outresetall */
 276         writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 277                &clock_manager_base->per_pll.vco);
 278
 279         /* deassert sdram outresetall */
 280         writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 281                &clock_manager_base->sdr_pll.vco);
 282
 283         /*
 284          * now that we've toggled outreset all, all the clocks
 285          * are aligned nicely; so we can change any phase.
 286          */
 287         cm_write_with_phase(cfg->ddrdqsclk,
 288                             (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
 289                             CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 290
 291         /* SDRAM DDR2XDQSCLK */
 292         cm_write_with_phase(cfg->ddr2xdqsclk,
 293                             (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
 294                             CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 295
 296         cm_write_with_phase(cfg->ddrdqclk,
 297                             (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
 298                             CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 299
 300         cm_write_with_phase(cfg->s2fuser2clk,
 301                             (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
 302                             CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 303
 304         /* Take all three PLLs out of bypass when safe mode is cleared. */
 305         cm_write_bypass(0);
 306
 307         /* clear safe mode */
 308         cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
 309
 310         /*
 311          * now that safe mode is clear with clocks gated
 312          * it safe to change the source mux for the flashes the the L4_MAIN
 313          */
 314         writel(cfg->persrc, &clock_manager_base->per_pll.src);
 315         writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
 316
 317         /* Now ungate non-hw-managed clocks */
 318         writel(~0, &clock_manager_base->main_pll.en);
 319         writel(~0, &clock_manager_base->per_pll.en);
 320         writel(~0, &clock_manager_base->sdr_pll.en);
 321 }
 322
 323 static unsigned int cm_get_main_vco_clk_hz(void)
 324 {
 325         uint32_t reg, clock;
 326
 327         /* get the main VCO clock */
 328         reg = readl(&clock_manager_base->main_pll.vco);
 329         clock = CONFIG_HPS_CLK_OSC1_HZ;
 330         clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
 331                   CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
 332         clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
 333                   CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
 334
 335         return clock;
 336 }
 337
 338 static unsigned int cm_get_per_vco_clk_hz(void)
 339 {
 340         uint32_t reg, clock = 0;
 341
 342         /* identify PER PLL clock source */
 343         reg = readl(&clock_manager_base->per_pll.vco);
 344         reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
 345               CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
 346         if (reg == CLKMGR_VCO_SSRC_EOSC1)
 347                 clock = CONFIG_HPS_CLK_OSC1_HZ;
 348         else if (reg == CLKMGR_VCO_SSRC_EOSC2)
 349                 clock = CONFIG_HPS_CLK_OSC2_HZ;
 350         else if (reg == CLKMGR_VCO_SSRC_F2S)
 351                 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 352
 353         /* get the PER VCO clock */
 354         reg = readl(&clock_manager_base->per_pll.vco);
 355         clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
 356                   CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
 357         clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
 358                   CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
 359
 360         return clock;
 361 }
 362
 363 unsigned long cm_get_mpu_clk_hz(void)
 364 {
 365         uint32_t reg, clock;
 366
 367         clock = cm_get_main_vco_clk_hz();
 368
 369         /* get the MPU clock */
 370         reg = readl(&clock_manager_base->altera.mpuclk);
 371         clock /= (reg + 1);
 372         reg = readl(&clock_manager_base->main_pll.mpuclk);
 373         clock /= (reg + 1);
 374         return clock;
 375 }
 376
 377 unsigned long cm_get_sdram_clk_hz(void)
 378 {
 379         uint32_t reg, clock = 0;
 380
 381         /* identify SDRAM PLL clock source */
 382         reg = readl(&clock_manager_base->sdr_pll.vco);
 383         reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
 384               CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
 385         if (reg == CLKMGR_VCO_SSRC_EOSC1)
 386                 clock = CONFIG_HPS_CLK_OSC1_HZ;
 387         else if (reg == CLKMGR_VCO_SSRC_EOSC2)
 388                 clock = CONFIG_HPS_CLK_OSC2_HZ;
 389         else if (reg == CLKMGR_VCO_SSRC_F2S)
 390                 clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
 391
 392         /* get the SDRAM VCO clock */
 393         reg = readl(&clock_manager_base->sdr_pll.vco);
 394         clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
 395                   CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
 396         clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
 397                   CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
 398
 399         /* get the SDRAM (DDR_DQS) clock */
 400         reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
 401         reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
 402               CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
 403         clock /= (reg + 1);
 404
 405         return clock;
 406 }
 407
 408 unsigned int cm_get_l4_sp_clk_hz(void)
 409 {
 410         uint32_t reg, clock = 0;
 411
 412         /* identify the source of L4 SP clock */
 413         reg = readl(&clock_manager_base->main_pll.l4src);
 414         reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
 415               CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
 416
 417         if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
 418                 clock = cm_get_main_vco_clk_hz();
 419
 420                 /* get the clock prior L4 SP divider (main clk) */
 421                 reg = readl(&clock_manager_base->altera.mainclk);
 422                 clock /= (reg + 1);
 423                 reg = readl(&clock_manager_base->main_pll.mainclk);
 424                 clock /= (reg + 1);
 425         } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
 426                 clock = cm_get_per_vco_clk_hz();
 427
 428                 /* get the clock prior L4 SP divider (periph_base_clk) */
 429                 reg = readl(&clock_manager_base->per_pll.perbaseclk);
 430                 clock /= (reg + 1);
 431         }
 432
 433         /* get the L4 SP clock which supplied to UART */
 434         reg = readl(&clock_manager_base->main_pll.maindiv);
 435         reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
 436               CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
 437         clock = clock / (1 << reg);
 438
 439         return clock;
 440 }
 441
 442 unsigned int cm_get_mmc_controller_clk_hz(void)
 443 {
 444         uint32_t reg, clock = 0;
 445
 446         /* identify the source of MMC clock */
 447         reg = readl(&clock_manager_base->per_pll.src);
 448         reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
 449               CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
 450
 451         if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
 452                 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 453         } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
 454                 clock = cm_get_main_vco_clk_hz();
 455
 456                 /* get the SDMMC clock */
 457                 reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
 458                 clock /= (reg + 1);
 459         } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
 460                 clock = cm_get_per_vco_clk_hz();
 461
 462                 /* get the SDMMC clock */
 463                 reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
 464                 clock /= (reg + 1);
 465         }
 466
 467         /* further divide by 4 as we have fixed divider at wrapper */
 468         clock /= 4;
 469         return clock;
 470 }
 471
 472 unsigned int cm_get_qspi_controller_clk_hz(void)
 473 {
 474         uint32_t reg, clock = 0;
 475
 476         /* identify the source of QSPI clock */
 477         reg = readl(&clock_manager_base->per_pll.src);
 478         reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
 479               CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
 480
 481         if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
 482                 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 483         } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
 484                 clock = cm_get_main_vco_clk_hz();
 485
 486                 /* get the qspi clock */
 487                 reg = readl(&clock_manager_base->main_pll.mainqspiclk);
 488                 clock /= (reg + 1);
 489         } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
 490                 clock = cm_get_per_vco_clk_hz();
 491
 492                 /* get the qspi clock */
 493                 reg = readl(&clock_manager_base->per_pll.perqspiclk);
 494                 clock /= (reg + 1);
 495         }
 496
 497         return clock;
 498 }
 499
 500 static void cm_print_clock_quick_summary(void)
 501 {
 502         printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
 503         printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
 504         printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
 505         printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
 506         printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
 507         printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
 508         printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
 509         printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
 510         printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
 511 }
 512
 513 int set_cpu_clk_info(void)
 514 {
 515         /* Calculate the clock frequencies required for drivers */
 516         cm_get_l4_sp_clk_hz();
 517         cm_get_mmc_controller_clk_hz();
 518
 519         gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
 520         gd->bd->bi_dsp_freq = 0;
 521         gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
 522
 523         return 0;
 524 }
 525
 526 int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 527 {
 528         cm_print_clock_quick_summary();
 529         return 0;
 530 }
 531
 532 U_BOOT_CMD(
 533         clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
 534         "display clocks",
 535         ""
 536 );