git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/socfpga/clock_manager.c

   1 /*
   2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clock_manager.h>
  10
  11 DECLARE_GLOBAL_DATA_PTR;
  12
  13 static const struct socfpga_clock_manager *clock_manager_base =
  14         (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  15
  16 #define CLKMGR_BYPASS_ENABLE    1
  17 #define CLKMGR_BYPASS_DISABLE   0
  18 #define CLKMGR_STAT_IDLE        0
  19 #define CLKMGR_STAT_BUSY        1
  20 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1            0
  21 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX        1
  22 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1            0
  23 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX        1
  24
  25 #define CLEAR_BGP_EN_PWRDN \
  26         (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
  27         CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
  28         CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
  29
  30 #define VCO_EN_BASE \
  31         (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
  32         CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
  33         CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
  34
  35 static void cm_wait_for_lock(uint32_t mask)
  36 {
  37         register uint32_t inter_val;
  38         do {
  39                 inter_val = readl(&clock_manager_base->inter) & mask;
  40         } while (inter_val != mask);
  41 }
  42
  43 /* function to poll in the fsm busy bit */
  44 static void cm_wait_for_fsm(void)
  45 {
  46         while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
  47                 ;
  48 }
  49
  50 /*
  51  * function to write the bypass register which requires a poll of the
  52  * busy bit
  53  */
  54 static void cm_write_bypass(uint32_t val)
  55 {
  56         writel(val, &clock_manager_base->bypass);
  57         cm_wait_for_fsm();
  58 }
  59
  60 /* function to write the ctrl register which requires a poll of the busy bit */
  61 static void cm_write_ctrl(uint32_t val)
  62 {
  63         writel(val, &clock_manager_base->ctrl);
  64         cm_wait_for_fsm();
  65 }
  66
  67 /* function to write a clock register that has phase information */
  68 static void cm_write_with_phase(uint32_t value,
  69                                 uint32_t reg_address, uint32_t mask)
  70 {
  71         /* poll until phase is zero */
  72         while (readl(reg_address) & mask)
  73                 ;
  74
  75         writel(value, reg_address);
  76
  77         while (readl(reg_address) & mask)
  78                 ;
  79 }
  80
  81 /*
  82  * Setup clocks while making no assumptions about previous state of the clocks.
  83  *
  84  * Start by being paranoid and gate all sw managed clocks
  85  * Put all plls in bypass
  86  * Put all plls VCO registers back to reset value (bandgap power down).
  87  * Put peripheral and main pll src to reset value to avoid glitch.
  88  * Delay 5 us.
  89  * Deassert bandgap power down and set numerator and denominator
  90  * Start 7 us timer.
  91  * set internal dividers
  92  * Wait for 7 us timer.
  93  * Enable plls
  94  * Set external dividers while plls are locking
  95  * Wait for pll lock
  96  * Assert/deassert outreset all.
  97  * Take all pll's out of bypass
  98  * Clear safe mode
  99  * set source main and peripheral clocks
 100  * Ungate clocks
 101  */
 102
 103 void cm_basic_init(const cm_config_t *cfg)
 104 {
 105         uint32_t start, timeout;
 106
 107         /* Start by being paranoid and gate all sw managed clocks */
 108
 109         /*
 110          * We need to disable nandclk
 111          * and then do another apb access before disabling
 112          * gatting off the rest of the periperal clocks.
 113          */
 114         writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
 115                 readl(&clock_manager_base->per_pll.en),
 116                 &clock_manager_base->per_pll.en);
 117
 118         /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
 119         writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
 120                 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
 121                 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
 122                 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
 123                 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
 124                 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
 125                 &clock_manager_base->main_pll.en);
 126
 127         writel(0, &clock_manager_base->sdr_pll.en);
 128
 129         /* now we can gate off the rest of the peripheral clocks */
 130         writel(0, &clock_manager_base->per_pll.en);
 131
 132         /* Put all plls in bypass */
 133         cm_write_bypass(
 134                 CLKMGR_BYPASS_PERPLLSRC_SET(
 135                 CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
 136                 CLKMGR_BYPASS_SDRPLLSRC_SET(
 137                 CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
 138                 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
 139                 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
 140                 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
 141
 142         /*
 143          * Put all plls VCO registers back to reset value.
 144          * Some code might have messed with them.
 145          */
 146         writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
 147                &clock_manager_base->main_pll.vco);
 148         writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
 149                &clock_manager_base->per_pll.vco);
 150         writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
 151                &clock_manager_base->sdr_pll.vco);
 152
 153         /*
 154          * The clocks to the flash devices and the L4_MAIN clocks can
 155          * glitch when coming out of safe mode if their source values
 156          * are different from their reset value.  So the trick it to
 157          * put them back to their reset state, and change input
 158          * after exiting safe mode but before ungating the clocks.
 159          */
 160         writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
 161                &clock_manager_base->per_pll.src);
 162         writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
 163                &clock_manager_base->main_pll.l4src);
 164
 165         /* read back for the required 5 us delay. */
 166         readl(&clock_manager_base->main_pll.vco);
 167         readl(&clock_manager_base->per_pll.vco);
 168         readl(&clock_manager_base->sdr_pll.vco);
 169
 170
 171         /*
 172          * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 173          * with numerator and denominator.
 174          */
 175         writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
 176                 CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
 177                 &clock_manager_base->main_pll.vco);
 178
 179         writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
 180                 CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
 181                 &clock_manager_base->per_pll.vco);
 182
 183         writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
 184                 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
 185                 cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
 186                 CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
 187                 &clock_manager_base->sdr_pll.vco);
 188
 189         /*
 190          * Time starts here
 191          * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
 192          */
 193         start = get_timer(0);
 194         /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
 195         timeout = 7;
 196
 197         /* main mpu */
 198         writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
 199
 200         /* main main clock */
 201         writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
 202
 203         /* main for dbg */
 204         writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
 205
 206         /* main for cfgs2fuser0clk */
 207         writel(cfg->cfg2fuser0clk,
 208                &clock_manager_base->main_pll.cfgs2fuser0clk);
 209
 210         /* Peri emac0 50 MHz default to RMII */
 211         writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
 212
 213         /* Peri emac1 50 MHz default to RMII */
 214         writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
 215
 216         /* Peri QSPI */
 217         writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
 218
 219         writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
 220
 221         /* Peri pernandsdmmcclk */
 222         writel(cfg->pernandsdmmcclk,
 223                &clock_manager_base->per_pll.pernandsdmmcclk);
 224
 225         /* Peri perbaseclk */
 226         writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
 227
 228         /* Peri s2fuser1clk */
 229         writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
 230
 231         /* 7 us must have elapsed before we can enable the VCO */
 232         while (get_timer(start) < timeout)
 233                 ;
 234
 235         /* Enable vco */
 236         /* main pll vco */
 237         writel(cfg->main_vco_base | VCO_EN_BASE,
 238                &clock_manager_base->main_pll.vco);
 239
 240         /* periferal pll */
 241         writel(cfg->peri_vco_base | VCO_EN_BASE,
 242                &clock_manager_base->per_pll.vco);
 243
 244         /* sdram pll vco */
 245         writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
 246                 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
 247                 cfg->sdram_vco_base | VCO_EN_BASE,
 248                 &clock_manager_base->sdr_pll.vco);
 249
 250         /* L3 MP and L3 SP */
 251         writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
 252
 253         writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
 254
 255         writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
 256
 257         /* L4 MP, L4 SP, can0, and can1 */
 258         writel(cfg->perdiv, &clock_manager_base->per_pll.div);
 259
 260         writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
 261
 262 #define LOCKED_MASK \
 263         (CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
 264         CLKMGR_INTER_PERPLLLOCKED_MASK  | \
 265         CLKMGR_INTER_MAINPLLLOCKED_MASK)
 266
 267         cm_wait_for_lock(LOCKED_MASK);
 268
 269         /* write the sdram clock counters before toggling outreset all */
 270         writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
 271                &clock_manager_base->sdr_pll.ddrdqsclk);
 272
 273         writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
 274                &clock_manager_base->sdr_pll.ddr2xdqsclk);
 275
 276         writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
 277                &clock_manager_base->sdr_pll.ddrdqclk);
 278
 279         writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
 280                &clock_manager_base->sdr_pll.s2fuser2clk);
 281
 282         /*
 283          * after locking, but before taking out of bypass
 284          * assert/deassert outresetall
 285          */
 286         uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
 287
 288         /* assert main outresetall */
 289         writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 290                &clock_manager_base->main_pll.vco);
 291
 292         uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
 293
 294         /* assert pheriph outresetall */
 295         writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 296                &clock_manager_base->per_pll.vco);
 297
 298         /* assert sdram outresetall */
 299         writel(cfg->sdram_vco_base | VCO_EN_BASE|
 300                 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
 301                 &clock_manager_base->sdr_pll.vco);
 302
 303         /* deassert main outresetall */
 304         writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 305                &clock_manager_base->main_pll.vco);
 306
 307         /* deassert pheriph outresetall */
 308         writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 309                &clock_manager_base->per_pll.vco);
 310
 311         /* deassert sdram outresetall */
 312         writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
 313                 cfg->sdram_vco_base | VCO_EN_BASE,
 314                 &clock_manager_base->sdr_pll.vco);
 315
 316         /*
 317          * now that we've toggled outreset all, all the clocks
 318          * are aligned nicely; so we can change any phase.
 319          */
 320         cm_write_with_phase(cfg->ddrdqsclk,
 321                             (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
 322                             CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 323
 324         /* SDRAM DDR2XDQSCLK */
 325         cm_write_with_phase(cfg->ddr2xdqsclk,
 326                             (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
 327                             CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 328
 329         cm_write_with_phase(cfg->ddrdqclk,
 330                             (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
 331                             CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 332
 333         cm_write_with_phase(cfg->s2fuser2clk,
 334                             (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
 335                             CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 336
 337         /* Take all three PLLs out of bypass when safe mode is cleared. */
 338         cm_write_bypass(
 339                 CLKMGR_BYPASS_PERPLLSRC_SET(
 340                         CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
 341                 CLKMGR_BYPASS_SDRPLLSRC_SET(
 342                         CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
 343                 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
 344                 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
 345                 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
 346
 347         /* clear safe mode */
 348         cm_write_ctrl(readl(&clock_manager_base->ctrl) |
 349                         CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
 350
 351         /*
 352          * now that safe mode is clear with clocks gated
 353          * it safe to change the source mux for the flashes the the L4_MAIN
 354          */
 355         writel(cfg->persrc, &clock_manager_base->per_pll.src);
 356         writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
 357
 358         /* Now ungate non-hw-managed clocks */
 359         writel(~0, &clock_manager_base->main_pll.en);
 360         writel(~0, &clock_manager_base->per_pll.en);
 361         writel(~0, &clock_manager_base->sdr_pll.en);
 362 }
 363
 364 static unsigned int cm_get_main_vco_clk_hz(void)
 365 {
 366         uint32_t reg, clock;
 367
 368         /* get the main VCO clock */
 369         reg = readl(&clock_manager_base->main_pll.vco);
 370         clock = CONFIG_HPS_CLK_OSC1_HZ /
 371                 (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
 372         clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
 373
 374         return clock;
 375 }
 376
 377 static unsigned int cm_get_per_vco_clk_hz(void)
 378 {
 379         uint32_t reg, clock = 0;
 380
 381         /* identify PER PLL clock source */
 382         reg = readl(&clock_manager_base->per_pll.vco);
 383         reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
 384         if (reg == CLKMGR_VCO_SSRC_EOSC1)
 385                 clock = CONFIG_HPS_CLK_OSC1_HZ;
 386         else if (reg == CLKMGR_VCO_SSRC_EOSC2)
 387                 clock = CONFIG_HPS_CLK_OSC2_HZ;
 388         else if (reg == CLKMGR_VCO_SSRC_F2S)
 389                 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 390
 391         /* get the PER VCO clock */
 392         reg = readl(&clock_manager_base->per_pll.vco);
 393         clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
 394         clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
 395
 396         return clock;
 397 }
 398
 399 unsigned long cm_get_mpu_clk_hz(void)
 400 {
 401         uint32_t reg, clock;
 402
 403         clock = cm_get_main_vco_clk_hz();
 404
 405         /* get the MPU clock */
 406         reg = readl(&clock_manager_base->altera.mpuclk);
 407         clock /= (reg + 1);
 408         reg = readl(&clock_manager_base->main_pll.mpuclk);
 409         clock /= (reg + 1);
 410         return clock;
 411 }
 412
 413 unsigned long cm_get_sdram_clk_hz(void)
 414 {
 415         uint32_t reg, clock = 0;
 416
 417         /* identify SDRAM PLL clock source */
 418         reg = readl(&clock_manager_base->sdr_pll.vco);
 419         reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
 420         if (reg == CLKMGR_VCO_SSRC_EOSC1)
 421                 clock = CONFIG_HPS_CLK_OSC1_HZ;
 422         else if (reg == CLKMGR_VCO_SSRC_EOSC2)
 423                 clock = CONFIG_HPS_CLK_OSC2_HZ;
 424         else if (reg == CLKMGR_VCO_SSRC_F2S)
 425                 clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
 426
 427         /* get the SDRAM VCO clock */
 428         reg = readl(&clock_manager_base->sdr_pll.vco);
 429         clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
 430         clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
 431
 432         /* get the SDRAM (DDR_DQS) clock */
 433         reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
 434         reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
 435         clock /= (reg + 1);
 436
 437         return clock;
 438 }
 439
 440 unsigned int cm_get_l4_sp_clk_hz(void)
 441 {
 442         uint32_t reg, clock = 0;
 443
 444         /* identify the source of L4 SP clock */
 445         reg = readl(&clock_manager_base->main_pll.l4src);
 446         reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
 447
 448         if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
 449                 clock = cm_get_main_vco_clk_hz();
 450
 451                 /* get the clock prior L4 SP divider (main clk) */
 452                 reg = readl(&clock_manager_base->altera.mainclk);
 453                 clock /= (reg + 1);
 454                 reg = readl(&clock_manager_base->main_pll.mainclk);
 455                 clock /= (reg + 1);
 456         } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
 457                 clock = cm_get_per_vco_clk_hz();
 458
 459                 /* get the clock prior L4 SP divider (periph_base_clk) */
 460                 reg = readl(&clock_manager_base->per_pll.perbaseclk);
 461                 clock /= (reg + 1);
 462         }
 463
 464         /* get the L4 SP clock which supplied to UART */
 465         reg = readl(&clock_manager_base->main_pll.maindiv);
 466         reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
 467         clock = clock / (1 << reg);
 468
 469         return clock;
 470 }
 471
 472 unsigned int cm_get_mmc_controller_clk_hz(void)
 473 {
 474         uint32_t reg, clock = 0;
 475
 476         /* identify the source of MMC clock */
 477         reg = readl(&clock_manager_base->per_pll.src);
 478         reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg);
 479
 480         if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
 481                 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 482         } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
 483                 clock = cm_get_main_vco_clk_hz();
 484
 485                 /* get the SDMMC clock */
 486                 reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
 487                 clock /= (reg + 1);
 488         } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
 489                 clock = cm_get_per_vco_clk_hz();
 490
 491                 /* get the SDMMC clock */
 492                 reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
 493                 clock /= (reg + 1);
 494         }
 495
 496         /* further divide by 4 as we have fixed divider at wrapper */
 497         clock /= 4;
 498         return clock;
 499 }
 500
 501 unsigned int cm_get_qspi_controller_clk_hz(void)
 502 {
 503         uint32_t reg, clock = 0;
 504
 505         /* identify the source of QSPI clock */
 506         reg = readl(&clock_manager_base->per_pll.src);
 507         reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg);
 508
 509         if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
 510                 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 511         } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
 512                 clock = cm_get_main_vco_clk_hz();
 513
 514                 /* get the qspi clock */
 515                 reg = readl(&clock_manager_base->main_pll.mainqspiclk);
 516                 clock /= (reg + 1);
 517         } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
 518                 clock = cm_get_per_vco_clk_hz();
 519
 520                 /* get the qspi clock */
 521                 reg = readl(&clock_manager_base->per_pll.perqspiclk);
 522                 clock /= (reg + 1);
 523         }
 524
 525         return clock;
 526 }
 527
 528 static void cm_print_clock_quick_summary(void)
 529 {
 530         printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
 531         printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
 532         printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
 533         printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
 534         printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
 535         printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
 536         printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
 537         printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
 538         printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
 539 }
 540
 541 int set_cpu_clk_info(void)
 542 {
 543         /* Calculate the clock frequencies required for drivers */
 544         cm_get_l4_sp_clk_hz();
 545         cm_get_mmc_controller_clk_hz();
 546
 547         gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
 548         gd->bd->bi_dsp_freq = 0;
 549         gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
 550
 551         return 0;
 552 }
 553
 554 int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 555 {
 556         cm_print_clock_quick_summary();
 557         return 0;
 558 }
 559
 560 U_BOOT_CMD(
 561         clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
 562         "display clocks",
 563         ""
 564 );