2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/freeze_controller.h>
11 #include <asm/arch/timer.h>
12 #include <asm/errno.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 static const struct socfpga_freeze_controller *freeze_controller_base =
17 (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
20 * Default state from cold reset is FREEZE_ALL; the global
21 * flag is set to TRUE to indicate the IO banks are frozen
23 static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
24 = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
25 FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
28 void sys_mgr_frzctrl_freeze_req(void)
30 u32 ioctrl_reg_offset;
35 /* select software FSM */
36 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
38 /* Freeze channel 0 to 2 */
39 for (channel_id = 0; channel_id <= 2; channel_id++) {
40 ioctrl_reg_offset = (u32)(
41 &freeze_controller_base->vioctrl +
42 (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
45 * Assert active low enrnsl, plniotri
49 SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
50 | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
51 | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
52 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
55 * Note: Delay for 20ns at min
56 * Assert active low bhniotri signal and de-assert
60 = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
61 | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
62 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
64 /* Set global flag to indicate channel is frozen */
65 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
68 /* Freeze channel 3 */
70 * Assert active low enrnsl, plniotri and
74 = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
75 | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
76 | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
77 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
80 * assert active low bhniotri & nfrzdrv signals,
81 * de-assert active high csrdone and assert
82 * active high frzreg and nfrzdrv signals
84 reg_value = readl(&freeze_controller_base->hioctrl);
86 = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
87 | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
89 = (reg_value & ~reg_cfg_mask)
90 | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
91 | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
92 writel(reg_value, &freeze_controller_base->hioctrl);
95 * assert active high reinit signal and de-assert
96 * active high pllbiasen signals
98 reg_value = readl(&freeze_controller_base->hioctrl);
101 ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
102 | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
103 writel(reg_value, &freeze_controller_base->hioctrl);
105 /* Set global flag to indicate channel is frozen */
106 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
109 /* Unfreeze/Thaw HPS IOs */
110 void sys_mgr_frzctrl_thaw_req(void)
112 u32 ioctrl_reg_offset;
117 /* select software FSM */
118 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
120 /* Thaw channel 0 to 2 */
121 for (channel_id = 0; channel_id <= 2; channel_id++) {
123 = (u32)(&freeze_controller_base->vioctrl
124 + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
127 * Assert active low bhniotri signal and
128 * de-assert active high csrdone
131 = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
132 | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
133 setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
136 * Note: Delay for 20ns at min
137 * de-assert active low plniotri and niotri signals
140 = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
141 | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
142 setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
145 * Note: Delay for 20ns at min
146 * de-assert active low enrnsl signal
148 setbits_le32(ioctrl_reg_offset,
149 SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
151 /* Set global flag to indicate channel is thawed */
152 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
156 /* de-assert active high reinit signal */
157 clrbits_le32(&freeze_controller_base->hioctrl,
158 SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
161 * Note: Delay for 40ns at min
162 * assert active high pllbiasen signals
164 setbits_le32(&freeze_controller_base->hioctrl,
165 SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
168 * Delay 1000 intosc. intosc is based on eosc1
169 * Use worst case which is fatest eosc1=50MHz, delay required
170 * is 1/50MHz * 1000 = 20us
175 * de-assert active low bhniotri signals,
176 * assert active high csrdone and nfrzdrv signal
178 reg_value = readl(&freeze_controller_base->hioctrl);
179 reg_value = (reg_value
180 | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
181 | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
182 & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
183 writel(reg_value, &freeze_controller_base->hioctrl);
187 * Use worst case which is fatest eosc1=50MHz, delay required
188 * is 1/50MHz * 33 = 660ns ~= 1us
192 /* de-assert active low plniotri and niotri signals */
194 = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
195 | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
197 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
200 * Note: Delay for 40ns at min
201 * de-assert active high frzreg signal
203 clrbits_le32(&freeze_controller_base->hioctrl,
204 SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
207 * Note: Delay for 40ns at min
208 * de-assert active low enrnsl signal
210 setbits_le32(&freeze_controller_base->hioctrl,
211 SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
213 /* Set global flag to indicate channel is thawed */
214 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;