2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 /* Set up the platform, once the cpu has been initialized */
15 #ifdef CONFIG_SPL_BUILD
17 * SPL : configure the remap (L3 NIC-301 GPV)
18 * so the on-chip RAM at lower memory instead ROM.
20 ldr r0, =SOCFPGA_L3REGS_ADDRESS
25 * U-Boot : configure the remap (L3 NIC-301 GPV)
26 * so the SDRAM at lower memory instead on-chip RAM.
28 ldr r0, =SOCFPGA_L3REGS_ADDRESS
32 /* Private components security */
35 * U-Boot : configure private timer, global timer and cpu
36 * component access as non secure for kernel stage (as required
45 #endif /* #ifdef CONFIG_SPL_BUILD */