2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/reset_manager.h>
14 #include <asm/arch/system_manager.h>
15 #include <asm/arch/dwmmc.h>
16 #include <asm/arch/nic301.h>
17 #include <asm/arch/scu.h>
18 #include <asm/pl310.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static struct pl310_regs *const pl310 =
23 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
24 static struct socfpga_system_manager *sysmgr_regs =
25 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
26 static struct socfpga_reset_manager *reset_manager_base =
27 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
28 static struct nic301_registers *nic301_regs =
29 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
30 static struct scu_registers *scu_regs =
31 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
35 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
39 void enable_caches(void)
41 #ifndef CONFIG_SYS_ICACHE_OFF
44 #ifndef CONFIG_SYS_DCACHE_OFF
50 * DesignWare Ethernet initialization
52 #ifdef CONFIG_DESIGNWARE_ETH
53 int cpu_eth_init(bd_t *bis)
55 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
56 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
57 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
58 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
60 #error "Incorrect CONFIG_EMAC_BASE value!"
63 /* Initialize EMAC. This needs to be done at least once per boot. */
66 * Putting the EMAC controller to reset when configuring the PHY
67 * interface select at System Manager
69 socfpga_emac_reset(1);
71 /* Clearing emac0 PHY interface select to 0 */
72 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
73 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
75 /* configure to PHY interface select choosed */
76 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
77 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
79 /* Release the EMAC controller from reset */
80 socfpga_emac_reset(0);
82 /* initialize and register the emac */
83 return designware_initialize(CONFIG_EMAC_BASE,
84 CONFIG_PHY_INTERFACE_MODE);
90 * Initializes MMC controllers.
91 * to override, implement board_mmc_init()
93 int cpu_mmc_init(bd_t *bis)
95 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
96 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
100 #if defined(CONFIG_DISPLAY_CPUINFO)
102 * Print CPU information
104 int print_cpuinfo(void)
106 puts("CPU: Altera SoCFPGA Platform\n");
111 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
112 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
113 int overwrite_console(void)
121 * FPGA programming support for SoC FPGA Cyclone V
123 static Altera_desc altera_fpga[] = {
128 fast_passive_parallel,
129 /* No limitation as additional data will be ignored */
131 /* No device function table */
133 /* Base interface address specified in driver */
135 /* No cookie implementation */
140 /* add device descriptor to FPGA device table */
141 static void socfpga_fpga_add(void)
145 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
146 fpga_add(fpga_altera, &altera_fpga[i]);
149 static inline void socfpga_fpga_add(void) {}
152 int arch_cpu_init(void)
154 #ifdef CONFIG_HW_WATCHDOG
156 * In case the watchdog is enabled, make sure to (re-)configure it
157 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
158 * timeout value is still active which might too short for Linux
164 * If the HW watchdog is NOT enabled, make sure it is not running,
165 * for example because it was enabled in the preloader. This might
166 * trigger a watchdog-triggered reboot of Linux kernel later.
168 socfpga_watchdog_reset();
175 * Convert all NIC-301 AMBA slaves from secure to non-secure
177 static void socfpga_nic301_slave_ns(void)
179 writel(0x1, &nic301_regs->lwhps2fpgaregs);
180 writel(0x1, &nic301_regs->hps2fpgaregs);
181 writel(0x1, &nic301_regs->acp);
182 writel(0x1, &nic301_regs->rom);
183 writel(0x1, &nic301_regs->ocram);
184 writel(0x1, &nic301_regs->sdrdata);
187 static uint32_t iswgrp_handoff[8];
189 int arch_early_init_r(void)
192 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
193 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
195 socfpga_bridges_reset(1);
196 socfpga_nic301_slave_ns();
199 * Private components security:
200 * U-Boot : configure private timer, global timer and cpu component
201 * access as non secure for kernel stage (as required by Linux)
203 setbits_le32(&scu_regs->sacr, 0xfff);
205 /* Configure the L2 controller to make SDRAM start at 0 */
206 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
207 writel(0x2, &nic301_regs->remap);
209 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
210 writel(0x1, &pl310->pl310_addr_filter_start);
213 /* Add device descriptor to FPGA device table */
216 #ifdef CONFIG_DESIGNWARE_SPI
217 /* Get Designware SPI controller out of reset */
218 socfpga_spim_enable();
224 static void socfpga_sdram_apply_static_cfg(void)
226 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
227 const uint32_t applymask = 0x8;
228 uint32_t val = readl(staticcfg) | applymask;
231 * SDRAM staticcfg register specific:
232 * When applying the register setting, the CPU must not access
233 * SDRAM. Luckily for us, we can abuse i-cache here to help us
234 * circumvent the SDRAM access issue. The idea is to make sure
235 * that the code is in one full i-cache line by branching past
236 * it and back. Once it is in the i-cache, we execute the core
237 * of the code and apply the register settings.
239 * The code below uses 7 instructions, while the Cortex-A9 has
240 * 32-byte cachelines, thus the limit is 8 instructions total.
251 : : "r"(val), "r"(staticcfg) : "memory", "cc");
254 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
257 return CMD_RET_USAGE;
262 case 'e': /* Enable */
263 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
264 socfpga_sdram_apply_static_cfg();
265 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
266 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
267 writel(iswgrp_handoff[1], &nic301_regs->remap);
269 case 'd': /* Disable */
270 writel(0, &sysmgr_regs->fpgaintfgrp_module);
271 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
272 socfpga_sdram_apply_static_cfg();
273 writel(0, &reset_manager_base->brg_mod_reset);
274 writel(1, &nic301_regs->remap);
277 return CMD_RET_USAGE;
284 bridge, 2, 1, do_bridge,
285 "SoCFPGA HPS FPGA bridge control",
286 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
287 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"