2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/dwmmc.h>
15 #include <asm/arch/nic301.h>
16 #include <asm/arch/scu.h>
17 #include <asm/pl310.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static struct pl310_regs *const pl310 =
22 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
23 static struct socfpga_system_manager *sysmgr_regs =
24 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
25 static struct nic301_registers *nic301_regs =
26 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
27 static struct scu_registers *scu_regs =
28 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
32 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
36 void enable_caches(void)
38 #ifndef CONFIG_SYS_ICACHE_OFF
41 #ifndef CONFIG_SYS_DCACHE_OFF
47 * DesignWare Ethernet initialization
49 #ifdef CONFIG_DESIGNWARE_ETH
50 int cpu_eth_init(bd_t *bis)
52 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
53 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
54 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
55 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
57 #error "Incorrect CONFIG_EMAC_BASE value!"
60 /* Initialize EMAC. This needs to be done at least once per boot. */
63 * Putting the EMAC controller to reset when configuring the PHY
64 * interface select at System Manager
66 socfpga_emac_reset(1);
68 /* Clearing emac0 PHY interface select to 0 */
69 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
70 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
72 /* configure to PHY interface select choosed */
73 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
74 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
76 /* Release the EMAC controller from reset */
77 socfpga_emac_reset(0);
79 /* initialize and register the emac */
80 return designware_initialize(CONFIG_EMAC_BASE,
81 CONFIG_PHY_INTERFACE_MODE);
87 * Initializes MMC controllers.
88 * to override, implement board_mmc_init()
90 int cpu_mmc_init(bd_t *bis)
92 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
93 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
97 #if defined(CONFIG_DISPLAY_CPUINFO)
99 * Print CPU information
101 int print_cpuinfo(void)
103 puts("CPU: Altera SoCFPGA Platform\n");
108 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
109 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
110 int overwrite_console(void)
118 * FPGA programming support for SoC FPGA Cyclone V
120 static Altera_desc altera_fpga[] = {
125 fast_passive_parallel,
126 /* No limitation as additional data will be ignored */
128 /* No device function table */
130 /* Base interface address specified in driver */
132 /* No cookie implementation */
137 /* add device descriptor to FPGA device table */
138 static void socfpga_fpga_add(void)
142 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
143 fpga_add(fpga_altera, &altera_fpga[i]);
146 static inline void socfpga_fpga_add(void) {}
149 int arch_cpu_init(void)
152 * If the HW watchdog is NOT enabled, make sure it is not running,
153 * for example because it was enabled in the preloader. This might
154 * trigger a watchdog-triggered reboot of Linux kernel later.
156 #ifndef CONFIG_HW_WATCHDOG
157 socfpga_watchdog_reset();
163 * Convert all NIC-301 AMBA slaves from secure to non-secure
165 static void socfpga_nic301_slave_ns(void)
167 writel(0x1, &nic301_regs->lwhps2fpgaregs);
168 writel(0x1, &nic301_regs->hps2fpgaregs);
169 writel(0x1, &nic301_regs->acp);
170 writel(0x1, &nic301_regs->rom);
171 writel(0x1, &nic301_regs->ocram);
172 writel(0x1, &nic301_regs->sdrdata);
175 int misc_init_r(void)
177 socfpga_bridges_reset(1);
178 socfpga_nic301_slave_ns();
181 * Private components security:
182 * U-Boot : configure private timer, global timer and cpu component
183 * access as non secure for kernel stage (as required by Linux)
185 setbits_le32(&scu_regs->sacr, 0xfff);
187 /* Configure the L2 controller to make SDRAM start at 0 */
188 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
189 writel(0x2, &nic301_regs->remap);
191 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
192 writel(0x1, &pl310->pl310_addr_filter_start);
195 /* Add device descriptor to FPGA device table */