2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/u-boot.h>
10 #include <asm/utils.h>
13 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/freeze_controller.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 u32 spl_boot_device(void)
22 return BOOT_DEVICE_RAM;
26 * Board initialization after bss clearance
28 void spl_board_init(void)
30 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
31 cm_config_t cm_default_cfg = {
34 CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
35 CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
36 CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
37 CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
38 CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
39 CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
40 CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
41 CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
42 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
43 CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
44 CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
45 CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
46 CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
47 CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
48 CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
49 CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
50 CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
51 CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
52 CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
53 CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
54 CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
55 CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
56 CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
57 CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
58 CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
59 CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
60 CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
61 CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
62 CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
63 CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
65 /* peripheral group */
67 CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
68 CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
69 CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
70 CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
71 CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
72 CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
73 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
74 CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
75 CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
76 CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
77 CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
78 CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
79 CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
80 CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
81 CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
82 CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
83 CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
84 CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
85 CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
86 CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
87 CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
88 CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
89 CLKMGR_PERPLLGRP_SRC_QSPI_SET(
90 CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
91 CLKMGR_PERPLLGRP_SRC_NAND_SET(
92 CONFIG_HPS_PERPLLGRP_SRC_NAND) |
93 CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
94 CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
98 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
99 CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
100 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
101 CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
102 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
103 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
104 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
105 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
106 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
107 CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
108 CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
109 CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
110 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
111 CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
112 CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
113 CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
116 debug("Freezing all I/O banks\n");
117 /* freeze all IO banks */
118 sys_mgr_frzctrl_freeze_req();
120 debug("Reconfigure Clock Manager\n");
121 /* reconfigure the PLLs */
122 cm_basic_init(&cm_default_cfg);
124 /* configure the pin muxing through system manager */
125 sysmgr_pinmux_init();
126 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
128 /* de-assert reset for peripherals and bridges based on handoff */
129 reset_deassert_peripherals_handoff();
131 debug("Unfreezing/Thaw all I/O banks\n");
132 /* unfreeze / thaw all IO banks */
133 sys_mgr_frzctrl_thaw_req();
135 /* enable console uart printing */
136 preloader_console_init();