2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
18 #include <asm/system.h>
19 #include <linux/linkage.h>
21 /*************************************************************************
23 * Startup Code (reset vector)
25 * do important init only if we don't start from memory!
26 * setup Memory and board specific bits prior to relocation.
27 * relocate armboot to ram
30 *************************************************************************/
33 .globl save_boot_params_ret
36 /* Allow the board to save important registers */
40 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
41 * except if in HYP mode already
44 and r1, r0, #0x1f @ mask mode bits
45 teq r1, #0x1a @ test for HYP mode
46 bicne r0, r0, #0x1f @ clear all mode bits
47 orrne r0, r0, #0x13 @ set SVC mode
48 orr r0, r0, #0xc0 @ disable FIQ and IRQ
53 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
54 * Continue to use ROM code vector only in OMAP4 spl)
56 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
57 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
58 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
60 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
62 /* Set vector address in CP15 VBAR register */
64 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
67 /* the mask ROM code should have PLL and others stable */
68 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
75 /*------------------------------------------------------------------------------*/
77 ENTRY(c_runtime_cpu_setup)
79 * If I-cache is enabled invalidate it
81 #ifndef CONFIG_SYS_ICACHE_OFF
82 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
83 mcr p15, 0, r0, c7, c10, 4 @ DSB
84 mcr p15, 0, r0, c7, c5, 4 @ ISB
89 ENDPROC(c_runtime_cpu_setup)
91 /*************************************************************************
93 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
94 * __attribute__((weak));
96 * Stack pointer is not yet initialized at this moment
97 * Don't save anything to stack even if compiled with -O0
99 *************************************************************************/
100 ENTRY(save_boot_params)
101 b save_boot_params_ret @ back to my caller
102 ENDPROC(save_boot_params)
103 .weak save_boot_params
105 /*************************************************************************
109 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
110 * CONFIG_SYS_ICACHE_OFF is defined.
112 *************************************************************************/
117 mov r0, #0 @ set up for MCR
118 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
119 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
120 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
121 mcr p15, 0, r0, c7, c10, 4 @ DSB
122 mcr p15, 0, r0, c7, c5, 4 @ ISB
125 * disable MMU stuff and caches
127 mrc p15, 0, r0, c1, c0, 0
128 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
129 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
130 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
131 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
132 #ifdef CONFIG_SYS_ICACHE_OFF
133 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
135 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
137 mcr p15, 0, r0, c1, c0, 0
139 #ifdef CONFIG_ARM_ERRATA_716044
140 mrc p15, 0, r0, c1, c0, 0 @ read system control register
141 orr r0, r0, #1 << 11 @ set bit #11
142 mcr p15, 0, r0, c1, c0, 0 @ write system control register
145 #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
146 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
147 orr r0, r0, #1 << 4 @ set bit #4
148 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
151 #ifdef CONFIG_ARM_ERRATA_743622
152 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
153 orr r0, r0, #1 << 6 @ set bit #6
154 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
157 #ifdef CONFIG_ARM_ERRATA_751472
158 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
159 orr r0, r0, #1 << 11 @ set bit #11
160 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
162 #ifdef CONFIG_ARM_ERRATA_761320
163 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
164 orr r0, r0, #1 << 21 @ set bit #21
165 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
168 mov r5, lr @ Store my Caller
169 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
170 mov r3, r1, lsr #20 @ get variant field
171 and r3, r3, #0xf @ r3 has CPU variant
172 and r4, r1, #0xf @ r4 has CPU revision
173 mov r2, r3, lsl #4 @ shift variant field for combined value
174 orr r2, r4, r2 @ r2 has combined CPU variant + revision
176 #ifdef CONFIG_ARM_ERRATA_798870
177 cmp r2, #0x30 @ Applies to lower than R3p0
178 bge skip_errata_798870 @ skip if not affected rev
179 cmp r2, #0x20 @ Applies to including and above R2p0
180 blt skip_errata_798870 @ skip if not affected rev
182 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
183 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
184 push {r1-r5} @ Save the cpu info registers
185 bl v7_arch_cp15_set_l2aux_ctrl
186 isb @ Recommended ISB after l2actlr update
187 pop {r1-r5} @ Restore the cpu info - fall through
191 #ifdef CONFIG_ARM_ERRATA_454179
192 cmp r2, #0x21 @ Only on < r2p1
193 bge skip_errata_454179
195 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
196 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
197 push {r1-r5} @ Save the cpu info registers
198 bl v7_arch_cp15_set_acr
199 pop {r1-r5} @ Restore the cpu info - fall through
204 #ifdef CONFIG_ARM_ERRATA_430973
205 cmp r2, #0x21 @ Only on < r2p1
206 bge skip_errata_430973
208 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
209 orr r0, r0, #(0x1 << 6) @ Set IBE bit
210 push {r1-r5} @ Save the cpu info registers
211 bl v7_arch_cp15_set_acr
212 pop {r1-r5} @ Restore the cpu info - fall through
217 #ifdef CONFIG_ARM_ERRATA_621766
218 cmp r2, #0x21 @ Only on < r2p1
219 bge skip_errata_621766
221 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
222 orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
223 push {r1-r5} @ Save the cpu info registers
224 bl v7_arch_cp15_set_acr
225 pop {r1-r5} @ Restore the cpu info - fall through
230 mov pc, r5 @ back to my caller
231 ENDPROC(cpu_init_cp15)
233 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
234 /*************************************************************************
236 * CPU_init_critical registers
238 * setup important registers
239 * setup memory timing
241 *************************************************************************/
244 * Jump to board specific initialization...
245 * The Mask ROM will have already initialized
246 * basic memory. Go here to bump up clock rate and handle
247 * wake up conditions.
249 b lowlevel_init @ go setup pll,mux,memory
250 ENDPROC(cpu_init_crit)