2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
19 #include <asm/system.h>
20 #include <linux/linkage.h>
24 ldr pc, _undefined_instruction
25 ldr pc, _software_interrupt
26 ldr pc, _prefetch_abort
31 #ifdef CONFIG_SPL_BUILD
32 _undefined_instruction: .word _undefined_instruction
33 _software_interrupt: .word _software_interrupt
34 _prefetch_abort: .word _prefetch_abort
35 _data_abort: .word _data_abort
36 _not_used: .word _not_used
39 _pad: .word 0x12345678 /* now 16*4=64 */
41 _undefined_instruction: .word undefined_instruction
42 _software_interrupt: .word software_interrupt
43 _prefetch_abort: .word prefetch_abort
44 _data_abort: .word data_abort
45 _not_used: .word not_used
48 _pad: .word 0x12345678 /* now 16*4=64 */
49 #endif /* CONFIG_SPL_BUILD */
54 .balignl 16,0xdeadbeef
55 /*************************************************************************
57 * Startup Code (reset vector)
59 * do important init only if we don't start from memory!
60 * setup Memory and board specific bits prior to relocation.
61 * relocate armboot to ram
64 *************************************************************************/
68 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
69 .word CONFIG_SPL_TEXT_BASE
71 .word CONFIG_SYS_TEXT_BASE
75 * These are defined in the board-specific linker script.
79 .word __bss_start - _start
83 .word __bss_end - _start
90 /* IRQ stack memory (calculated at run-time) */
91 .globl IRQ_STACK_START
95 /* IRQ stack memory (calculated at run-time) */
96 .globl FIQ_STACK_START
101 /* IRQ stack memory (calculated at run-time) + 8 bytes */
102 .globl IRQ_STACK_START_IN
107 * the actual reset code
113 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
114 * except if in HYP mode already
117 and r1, r0, #0x1f @ mask mode bits
118 teq r1, #0x1a @ test for HYP mode
119 bicne r0, r0, #0x1f @ clear all mode bits
120 orrne r0, r0, #0x13 @ set SVC mode
121 orr r0, r0, #0xc0 @ disable FIQ and IRQ
126 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
127 * Continue to use ROM code vector only in OMAP4 spl)
129 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
130 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
131 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
132 bic r0, #CR_V @ V = 0
133 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
135 /* Set vector address in CP15 VBAR register */
137 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
140 /* the mask ROM code should have PLL and others stable */
141 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
148 /*------------------------------------------------------------------------------*/
150 ENTRY(c_runtime_cpu_setup)
152 * If I-cache is enabled invalidate it
154 #ifndef CONFIG_SYS_ICACHE_OFF
155 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
156 mcr p15, 0, r0, c7, c10, 4 @ DSB
157 mcr p15, 0, r0, c7, c5, 4 @ ISB
162 /* Set vector address in CP15 VBAR register */
164 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
168 ENDPROC(c_runtime_cpu_setup)
170 /*************************************************************************
172 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
173 * __attribute__((weak));
175 * Stack pointer is not yet initialized at this moment
176 * Don't save anything to stack even if compiled with -O0
178 *************************************************************************/
179 ENTRY(save_boot_params)
180 bx lr @ back to my caller
181 ENDPROC(save_boot_params)
182 .weak save_boot_params
184 /*************************************************************************
188 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
189 * CONFIG_SYS_ICACHE_OFF is defined.
191 *************************************************************************/
196 mov r0, #0 @ set up for MCR
197 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
198 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
199 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
200 mcr p15, 0, r0, c7, c10, 4 @ DSB
201 mcr p15, 0, r0, c7, c5, 4 @ ISB
204 * disable MMU stuff and caches
206 mrc p15, 0, r0, c1, c0, 0
207 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
208 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
209 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
210 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
211 #ifdef CONFIG_SYS_ICACHE_OFF
212 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
214 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
216 mcr p15, 0, r0, c1, c0, 0
218 #ifdef CONFIG_ARM_ERRATA_716044
219 mrc p15, 0, r0, c1, c0, 0 @ read system control register
220 orr r0, r0, #1 << 11 @ set bit #11
221 mcr p15, 0, r0, c1, c0, 0 @ write system control register
224 #ifdef CONFIG_ARM_ERRATA_742230
225 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
226 orr r0, r0, #1 << 4 @ set bit #4
227 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
230 #ifdef CONFIG_ARM_ERRATA_743622
231 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
232 orr r0, r0, #1 << 6 @ set bit #6
233 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
236 #ifdef CONFIG_ARM_ERRATA_751472
237 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
238 orr r0, r0, #1 << 11 @ set bit #11
239 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
242 mov pc, lr @ back to my caller
243 ENDPROC(cpu_init_cp15)
245 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
246 /*************************************************************************
248 * CPU_init_critical registers
250 * setup important registers
251 * setup memory timing
253 *************************************************************************/
256 * Jump to board specific initialization...
257 * The Mask ROM will have already initialized
258 * basic memory. Go here to bump up clock rate and handle
259 * wake up conditions.
261 b lowlevel_init @ go setup pll,mux,memory
262 ENDPROC(cpu_init_crit)
265 #ifndef CONFIG_SPL_BUILD
267 *************************************************************************
271 *************************************************************************
276 #define S_FRAME_SIZE 72
298 #define MODE_SVC 0x13
302 * use bad_save_user_regs for abort/prefetch/undef/swi ...
303 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
306 .macro bad_save_user_regs
307 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
309 stmia sp, {r0 - r12} @ Save user registers (now in
311 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
313 ldmia r2, {r2 - r3} @ get values for "aborted" pc
314 @ and cpsr (into parm regs)
315 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
319 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
320 mov r0, sp @ save current stack into r0
324 .macro irq_save_user_regs
325 sub sp, sp, #S_FRAME_SIZE
326 stmia sp, {r0 - r12} @ Calling r0-r12
327 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
328 @ a reserved stack spot would
330 stmdb r8, {sp, lr}^ @ Calling SP, LR
331 str lr, [r8, #0] @ Save calling PC
333 str r6, [r8, #4] @ Save CPSR
334 str r0, [r8, #8] @ Save OLD_R0
338 .macro irq_restore_user_regs
339 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
341 ldr lr, [sp, #S_PC] @ Get PC
342 add sp, sp, #S_FRAME_SIZE
343 subs pc, lr, #4 @ return & move spsr_svc into
348 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
351 str lr, [r13] @ save caller lr in position 0
353 mrs lr, spsr @ get the spsr
354 str lr, [r13, #4] @ save spsr in position 1 of
357 mov r13, #MODE_SVC @ prepare SVC-Mode
359 msr spsr, r13 @ switch modes, make sure
361 mov lr, pc @ capture return pc
362 movs pc, lr @ jump to next instruction &
366 .macro get_bad_stack_swi
367 sub r13, r13, #4 @ space on current stack for
369 str r0, [r13] @ save R0's value.
370 ldr r0, IRQ_STACK_START_IN @ get data regions start
371 @ spots for abort stack
372 str lr, [r0] @ save caller lr in position 0
374 mrs lr, spsr @ get the spsr
375 str lr, [r0, #4] @ save spsr in position 1 of
377 ldr lr, [r0] @ restore lr
378 ldr r0, [r13] @ restore r0
379 add r13, r13, #4 @ pop stack entry
382 .macro get_irq_stack @ setup IRQ stack
383 ldr sp, IRQ_STACK_START
386 .macro get_fiq_stack @ setup FIQ stack
387 ldr sp, FIQ_STACK_START
394 undefined_instruction:
397 bl do_undefined_instruction
403 bl do_software_interrupt
423 #ifdef CONFIG_USE_IRQ
430 irq_restore_user_regs
435 /* someone ought to write a more effective fiq_save_user_regs */
438 irq_restore_user_regs
454 #endif /* CONFIG_USE_IRQ */
455 #endif /* CONFIG_SPL_BUILD */