2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
18 #include <asm/system.h>
19 #include <linux/linkage.h>
21 /*************************************************************************
23 * Startup Code (reset vector)
25 * Do important init only if we don't start from memory!
26 * Setup memory and board specific bits prior to relocation.
27 * Relocate armboot to ram. Setup stack.
29 *************************************************************************/
32 .globl save_boot_params_ret
35 /* Allow the board to save important registers */
39 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
40 * except if in HYP mode already
43 and r1, r0, #0x1f @ mask mode bits
44 teq r1, #0x1a @ test for HYP mode
45 bicne r0, r0, #0x1f @ clear all mode bits
46 orrne r0, r0, #0x13 @ set SVC mode
47 orr r0, r0, #0xc0 @ disable FIQ and IRQ
52 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
53 * Continue to use ROM code vector only in OMAP4 spl)
55 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
56 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
57 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
59 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
61 /* Set vector address in CP15 VBAR register */
63 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
66 /* the mask ROM code should have PLL and others stable */
67 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
74 /*------------------------------------------------------------------------------*/
76 ENTRY(c_runtime_cpu_setup)
78 * If I-cache is enabled invalidate it
80 #ifndef CONFIG_SYS_ICACHE_OFF
81 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
82 mcr p15, 0, r0, c7, c10, 4 @ DSB
83 mcr p15, 0, r0, c7, c5, 4 @ ISB
88 ENDPROC(c_runtime_cpu_setup)
90 /*************************************************************************
92 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
93 * __attribute__((weak));
95 * Stack pointer is not yet initialized at this moment
96 * Don't save anything to stack even if compiled with -O0
98 *************************************************************************/
99 ENTRY(save_boot_params)
100 b save_boot_params_ret @ back to my caller
101 ENDPROC(save_boot_params)
102 .weak save_boot_params
104 /*************************************************************************
108 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
109 * CONFIG_SYS_ICACHE_OFF is defined.
111 *************************************************************************/
116 mov r0, #0 @ set up for MCR
117 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
119 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
120 mcr p15, 0, r0, c7, c10, 4 @ DSB
121 mcr p15, 0, r0, c7, c5, 4 @ ISB
124 * disable MMU stuff and caches
126 mrc p15, 0, r0, c1, c0, 0
127 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
128 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
129 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
130 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
131 #ifdef CONFIG_SYS_ICACHE_OFF
132 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
134 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
136 mcr p15, 0, r0, c1, c0, 0
138 #ifdef CONFIG_ARM_ERRATA_716044
139 mrc p15, 0, r0, c1, c0, 0 @ read system control register
140 orr r0, r0, #1 << 11 @ set bit #11
141 mcr p15, 0, r0, c1, c0, 0 @ write system control register
144 #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
145 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
146 orr r0, r0, #1 << 4 @ set bit #4
147 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
150 #ifdef CONFIG_ARM_ERRATA_743622
151 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
152 orr r0, r0, #1 << 6 @ set bit #6
153 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
156 #ifdef CONFIG_ARM_ERRATA_751472
157 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
158 orr r0, r0, #1 << 11 @ set bit #11
159 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
161 #ifdef CONFIG_ARM_ERRATA_761320
162 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
163 orr r0, r0, #1 << 21 @ set bit #21
164 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
167 mov r5, lr @ Store my Caller
168 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
169 mov r3, r1, lsr #20 @ get variant field
170 and r3, r3, #0xf @ r3 has CPU variant
171 and r4, r1, #0xf @ r4 has CPU revision
172 mov r2, r3, lsl #4 @ shift variant field for combined value
173 orr r2, r4, r2 @ r2 has combined CPU variant + revision
175 #ifdef CONFIG_ARM_ERRATA_798870
176 cmp r2, #0x30 @ Applies to lower than R3p0
177 bge skip_errata_798870 @ skip if not affected rev
178 cmp r2, #0x20 @ Applies to including and above R2p0
179 blt skip_errata_798870 @ skip if not affected rev
181 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
182 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
183 push {r1-r5} @ Save the cpu info registers
184 bl v7_arch_cp15_set_l2aux_ctrl
185 isb @ Recommended ISB after l2actlr update
186 pop {r1-r5} @ Restore the cpu info - fall through
190 #ifdef CONFIG_ARM_ERRATA_801819
191 cmp r2, #0x24 @ Applies to lt including R2p4
192 bgt skip_errata_801819 @ skip if not affected rev
193 cmp r2, #0x20 @ Applies to including and above R2p0
194 blt skip_errata_801819 @ skip if not affected rev
195 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
196 and r0, r0, #1 << 3 @ check REVIDR[3]
198 beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
200 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
201 orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
202 @ lines allocate in the L1 or L2 cache.
203 orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
204 @ lines allocate in the L1 cache.
205 push {r1-r5} @ Save the cpu info registers
206 bl v7_arch_cp15_set_acr
207 pop {r1-r5} @ Restore the cpu info - fall through
211 #ifdef CONFIG_ARM_ERRATA_454179
212 cmp r2, #0x21 @ Only on < r2p1
213 bge skip_errata_454179
215 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
216 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
217 push {r1-r5} @ Save the cpu info registers
218 bl v7_arch_cp15_set_acr
219 pop {r1-r5} @ Restore the cpu info - fall through
224 #ifdef CONFIG_ARM_ERRATA_430973
225 cmp r2, #0x21 @ Only on < r2p1
226 bge skip_errata_430973
228 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
229 orr r0, r0, #(0x1 << 6) @ Set IBE bit
230 push {r1-r5} @ Save the cpu info registers
231 bl v7_arch_cp15_set_acr
232 pop {r1-r5} @ Restore the cpu info - fall through
237 #ifdef CONFIG_ARM_ERRATA_621766
238 cmp r2, #0x21 @ Only on < r2p1
239 bge skip_errata_621766
241 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
242 orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
243 push {r1-r5} @ Save the cpu info registers
244 bl v7_arch_cp15_set_acr
245 pop {r1-r5} @ Restore the cpu info - fall through
250 mov pc, r5 @ back to my caller
251 ENDPROC(cpu_init_cp15)
253 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
254 /*************************************************************************
256 * CPU_init_critical registers
258 * setup important registers
259 * setup memory timing
261 *************************************************************************/
264 * Jump to board specific initialization...
265 * The Mask ROM will have already initialized
266 * basic memory. Go here to bump up clock rate and handle
267 * wake up conditions.
269 b lowlevel_init @ go setup pll,mux,memory
270 ENDPROC(cpu_init_crit)