2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
35 #include <asm/system.h>
36 #include <linux/linkage.h>
40 ldr pc, _undefined_instruction
41 ldr pc, _software_interrupt
42 ldr pc, _prefetch_abort
47 #ifdef CONFIG_SPL_BUILD
48 _undefined_instruction: .word _undefined_instruction
49 _software_interrupt: .word _software_interrupt
50 _prefetch_abort: .word _prefetch_abort
51 _data_abort: .word _data_abort
52 _not_used: .word _not_used
55 _pad: .word 0x12345678 /* now 16*4=64 */
57 _undefined_instruction: .word undefined_instruction
58 _software_interrupt: .word software_interrupt
59 _prefetch_abort: .word prefetch_abort
60 _data_abort: .word data_abort
61 _not_used: .word not_used
64 _pad: .word 0x12345678 /* now 16*4=64 */
65 #endif /* CONFIG_SPL_BUILD */
70 .balignl 16,0xdeadbeef
71 /*************************************************************************
73 * Startup Code (reset vector)
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
80 *************************************************************************/
84 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
85 .word CONFIG_SPL_TEXT_BASE
87 .word CONFIG_SYS_TEXT_BASE
91 * These are defined in the board-specific linker script.
95 .word __bss_start - _start
97 .globl _image_copy_end_ofs
99 .word __image_copy_end - _start
103 .word __bss_end - _start
109 #ifdef CONFIG_USE_IRQ
110 /* IRQ stack memory (calculated at run-time) */
111 .globl IRQ_STACK_START
115 /* IRQ stack memory (calculated at run-time) */
116 .globl FIQ_STACK_START
121 /* IRQ stack memory (calculated at run-time) + 8 bytes */
122 .globl IRQ_STACK_START_IN
127 * the actual reset code
133 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
134 * except if in HYP mode already
137 and r1, r0, #0x1f @ mask mode bits
138 teq r1, #0x1a @ test for HYP mode
139 bicne r0, r0, #0x1f @ clear all mode bits
140 orrne r0, r0, #0x13 @ set SVC mode
141 orr r0, r0, #0xc0 @ disable FIQ and IRQ
146 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
147 * Continue to use ROM code vector only in OMAP4 spl)
149 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
150 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
151 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
152 bic r0, #CR_V @ V = 0
153 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
155 /* Set vector address in CP15 VBAR register */
157 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
160 /* the mask ROM code should have PLL and others stable */
161 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
168 /*------------------------------------------------------------------------------*/
170 #ifndef CONFIG_SPL_BUILD
172 * void relocate_code(addr_moni)
174 * This function relocates the monitor code.
177 mov r6, r0 /* save addr of destination */
180 subs r9, r6, r0 /* r9 <- relocation offset */
181 beq relocate_done /* skip relocation */
182 mov r1, r6 /* r1 <- scratch for copy_loop */
183 ldr r3, _image_copy_end_ofs
184 add r2, r0, r3 /* r2 <- source end address */
187 ldmia r0!, {r10-r11} /* copy from source address [r0] */
188 stmia r1!, {r10-r11} /* copy to target address [r1] */
189 cmp r0, r2 /* until source end address [r2] */
193 * fix .rel.dyn relocations
195 ldr r0, _TEXT_BASE /* r0 <- Text base */
196 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
197 add r10, r10, r0 /* r10 <- sym table in FLASH */
198 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
199 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
200 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
201 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
203 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
204 add r0, r0, r9 /* r0 <- location to fix up in RAM */
207 cmp r7, #23 /* relative fixup? */
209 cmp r7, #2 /* absolute fixup? */
211 /* ignore unknown type of fixup */
214 /* absolute fix: set location to (offset) symbol value */
215 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
216 add r1, r10, r1 /* r1 <- address of symbol in table */
217 ldr r1, [r1, #4] /* r1 <- symbol value */
218 add r1, r1, r9 /* r1 <- relocated sym addr */
221 /* relative fix: increase location by offset */
226 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
235 .word __rel_dyn_start - _start
237 .word __rel_dyn_end - _start
239 .word __dynsym_start - _start
240 ENDPROC(relocate_code)
244 ENTRY(c_runtime_cpu_setup)
246 * If I-cache is enabled invalidate it
248 #ifndef CONFIG_SYS_ICACHE_OFF
249 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
250 mcr p15, 0, r0, c7, c10, 4 @ DSB
251 mcr p15, 0, r0, c7, c5, 4 @ ISB
256 #if !defined(CONFIG_TEGRA)
257 /* Set vector address in CP15 VBAR register */
259 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
264 ENDPROC(c_runtime_cpu_setup)
266 /*************************************************************************
268 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
269 * __attribute__((weak));
271 * Stack pointer is not yet initialized at this moment
272 * Don't save anything to stack even if compiled with -O0
274 *************************************************************************/
275 ENTRY(save_boot_params)
276 bx lr @ back to my caller
277 ENDPROC(save_boot_params)
278 .weak save_boot_params
280 /*************************************************************************
284 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
285 * CONFIG_SYS_ICACHE_OFF is defined.
287 *************************************************************************/
292 mov r0, #0 @ set up for MCR
293 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
294 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
295 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
296 mcr p15, 0, r0, c7, c10, 4 @ DSB
297 mcr p15, 0, r0, c7, c5, 4 @ ISB
300 * disable MMU stuff and caches
302 mrc p15, 0, r0, c1, c0, 0
303 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
304 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
305 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
306 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
307 #ifdef CONFIG_SYS_ICACHE_OFF
308 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
310 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
312 mcr p15, 0, r0, c1, c0, 0
314 #ifdef CONFIG_ARM_ERRATA_716044
315 mrc p15, 0, r0, c1, c0, 0 @ read system control register
316 orr r0, r0, #1 << 11 @ set bit #11
317 mcr p15, 0, r0, c1, c0, 0 @ write system control register
320 #ifdef CONFIG_ARM_ERRATA_742230
321 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
322 orr r0, r0, #1 << 4 @ set bit #4
323 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
326 #ifdef CONFIG_ARM_ERRATA_743622
327 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
328 orr r0, r0, #1 << 6 @ set bit #6
329 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
332 #ifdef CONFIG_ARM_ERRATA_751472
333 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
334 orr r0, r0, #1 << 11 @ set bit #11
335 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
338 mov pc, lr @ back to my caller
339 ENDPROC(cpu_init_cp15)
341 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
342 /*************************************************************************
344 * CPU_init_critical registers
346 * setup important registers
347 * setup memory timing
349 *************************************************************************/
352 * Jump to board specific initialization...
353 * The Mask ROM will have already initialized
354 * basic memory. Go here to bump up clock rate and handle
355 * wake up conditions.
357 b lowlevel_init @ go setup pll,mux,memory
358 ENDPROC(cpu_init_crit)
361 #ifndef CONFIG_SPL_BUILD
363 *************************************************************************
367 *************************************************************************
372 #define S_FRAME_SIZE 72
394 #define MODE_SVC 0x13
398 * use bad_save_user_regs for abort/prefetch/undef/swi ...
399 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
402 .macro bad_save_user_regs
403 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
405 stmia sp, {r0 - r12} @ Save user registers (now in
407 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
409 ldmia r2, {r2 - r3} @ get values for "aborted" pc
410 @ and cpsr (into parm regs)
411 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
415 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
416 mov r0, sp @ save current stack into r0
420 .macro irq_save_user_regs
421 sub sp, sp, #S_FRAME_SIZE
422 stmia sp, {r0 - r12} @ Calling r0-r12
423 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
424 @ a reserved stack spot would
426 stmdb r8, {sp, lr}^ @ Calling SP, LR
427 str lr, [r8, #0] @ Save calling PC
429 str r6, [r8, #4] @ Save CPSR
430 str r0, [r8, #8] @ Save OLD_R0
434 .macro irq_restore_user_regs
435 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
437 ldr lr, [sp, #S_PC] @ Get PC
438 add sp, sp, #S_FRAME_SIZE
439 subs pc, lr, #4 @ return & move spsr_svc into
444 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
447 str lr, [r13] @ save caller lr in position 0
449 mrs lr, spsr @ get the spsr
450 str lr, [r13, #4] @ save spsr in position 1 of
453 mov r13, #MODE_SVC @ prepare SVC-Mode
455 msr spsr, r13 @ switch modes, make sure
457 mov lr, pc @ capture return pc
458 movs pc, lr @ jump to next instruction &
462 .macro get_bad_stack_swi
463 sub r13, r13, #4 @ space on current stack for
465 str r0, [r13] @ save R0's value.
466 ldr r0, IRQ_STACK_START_IN @ get data regions start
467 @ spots for abort stack
468 str lr, [r0] @ save caller lr in position 0
470 mrs lr, spsr @ get the spsr
471 str lr, [r0, #4] @ save spsr in position 1 of
473 ldr lr, [r0] @ restore lr
474 ldr r0, [r13] @ restore r0
475 add r13, r13, #4 @ pop stack entry
478 .macro get_irq_stack @ setup IRQ stack
479 ldr sp, IRQ_STACK_START
482 .macro get_fiq_stack @ setup FIQ stack
483 ldr sp, FIQ_STACK_START
490 undefined_instruction:
493 bl do_undefined_instruction
499 bl do_software_interrupt
519 #ifdef CONFIG_USE_IRQ
526 irq_restore_user_regs
531 /* someone ought to write a more effective fiq_save_user_regs */
534 irq_restore_user_regs
550 #endif /* CONFIG_USE_IRQ */
551 #endif /* CONFIG_SPL_BUILD */