2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
35 #include <asm/system.h>
36 #include <linux/linkage.h>
40 ldr pc, _undefined_instruction
41 ldr pc, _software_interrupt
42 ldr pc, _prefetch_abort
47 #ifdef CONFIG_SPL_BUILD
48 _undefined_instruction: .word _undefined_instruction
49 _software_interrupt: .word _software_interrupt
50 _prefetch_abort: .word _prefetch_abort
51 _data_abort: .word _data_abort
52 _not_used: .word _not_used
55 _pad: .word 0x12345678 /* now 16*4=64 */
57 _undefined_instruction: .word undefined_instruction
58 _software_interrupt: .word software_interrupt
59 _prefetch_abort: .word prefetch_abort
60 _data_abort: .word data_abort
61 _not_used: .word not_used
64 _pad: .word 0x12345678 /* now 16*4=64 */
65 #endif /* CONFIG_SPL_BUILD */
70 .balignl 16,0xdeadbeef
71 /*************************************************************************
73 * Startup Code (reset vector)
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
80 *************************************************************************/
84 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
85 .word CONFIG_SPL_TEXT_BASE
87 .word CONFIG_SYS_TEXT_BASE
91 * These are defined in the board-specific linker script.
95 .word __bss_start - _start
99 .word __bss_end - _start
105 #ifdef CONFIG_USE_IRQ
106 /* IRQ stack memory (calculated at run-time) */
107 .globl IRQ_STACK_START
111 /* IRQ stack memory (calculated at run-time) */
112 .globl FIQ_STACK_START
117 /* IRQ stack memory (calculated at run-time) + 8 bytes */
118 .globl IRQ_STACK_START_IN
123 * the actual reset code
129 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
130 * except if in HYP mode already
133 and r1, r0, #0x1f @ mask mode bits
134 teq r1, #0x1a @ test for HYP mode
135 bicne r0, r0, #0x1f @ clear all mode bits
136 orrne r0, r0, #0x13 @ set SVC mode
137 orr r0, r0, #0xc0 @ disable FIQ and IRQ
142 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
143 * Continue to use ROM code vector only in OMAP4 spl)
145 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
146 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
147 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
148 bic r0, #CR_V @ V = 0
149 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
151 /* Set vector address in CP15 VBAR register */
153 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
156 /* the mask ROM code should have PLL and others stable */
157 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
164 /*------------------------------------------------------------------------------*/
166 ENTRY(c_runtime_cpu_setup)
168 * If I-cache is enabled invalidate it
170 #ifndef CONFIG_SYS_ICACHE_OFF
171 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
172 mcr p15, 0, r0, c7, c10, 4 @ DSB
173 mcr p15, 0, r0, c7, c5, 4 @ ISB
178 /* Set vector address in CP15 VBAR register */
180 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
184 ENDPROC(c_runtime_cpu_setup)
186 /*************************************************************************
188 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
189 * __attribute__((weak));
191 * Stack pointer is not yet initialized at this moment
192 * Don't save anything to stack even if compiled with -O0
194 *************************************************************************/
195 ENTRY(save_boot_params)
196 bx lr @ back to my caller
197 ENDPROC(save_boot_params)
198 .weak save_boot_params
200 /*************************************************************************
204 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
205 * CONFIG_SYS_ICACHE_OFF is defined.
207 *************************************************************************/
212 mov r0, #0 @ set up for MCR
213 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
214 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
215 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
216 mcr p15, 0, r0, c7, c10, 4 @ DSB
217 mcr p15, 0, r0, c7, c5, 4 @ ISB
220 * disable MMU stuff and caches
222 mrc p15, 0, r0, c1, c0, 0
223 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
224 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
225 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
226 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
227 #ifdef CONFIG_SYS_ICACHE_OFF
228 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
230 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
232 mcr p15, 0, r0, c1, c0, 0
234 #ifdef CONFIG_ARM_ERRATA_716044
235 mrc p15, 0, r0, c1, c0, 0 @ read system control register
236 orr r0, r0, #1 << 11 @ set bit #11
237 mcr p15, 0, r0, c1, c0, 0 @ write system control register
240 #ifdef CONFIG_ARM_ERRATA_742230
241 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
242 orr r0, r0, #1 << 4 @ set bit #4
243 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
246 #ifdef CONFIG_ARM_ERRATA_743622
247 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
248 orr r0, r0, #1 << 6 @ set bit #6
249 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
252 #ifdef CONFIG_ARM_ERRATA_751472
253 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
254 orr r0, r0, #1 << 11 @ set bit #11
255 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
258 mov pc, lr @ back to my caller
259 ENDPROC(cpu_init_cp15)
261 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
262 /*************************************************************************
264 * CPU_init_critical registers
266 * setup important registers
267 * setup memory timing
269 *************************************************************************/
272 * Jump to board specific initialization...
273 * The Mask ROM will have already initialized
274 * basic memory. Go here to bump up clock rate and handle
275 * wake up conditions.
277 b lowlevel_init @ go setup pll,mux,memory
278 ENDPROC(cpu_init_crit)
281 #ifndef CONFIG_SPL_BUILD
283 *************************************************************************
287 *************************************************************************
292 #define S_FRAME_SIZE 72
314 #define MODE_SVC 0x13
318 * use bad_save_user_regs for abort/prefetch/undef/swi ...
319 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
322 .macro bad_save_user_regs
323 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
325 stmia sp, {r0 - r12} @ Save user registers (now in
327 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
329 ldmia r2, {r2 - r3} @ get values for "aborted" pc
330 @ and cpsr (into parm regs)
331 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
335 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
336 mov r0, sp @ save current stack into r0
340 .macro irq_save_user_regs
341 sub sp, sp, #S_FRAME_SIZE
342 stmia sp, {r0 - r12} @ Calling r0-r12
343 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
344 @ a reserved stack spot would
346 stmdb r8, {sp, lr}^ @ Calling SP, LR
347 str lr, [r8, #0] @ Save calling PC
349 str r6, [r8, #4] @ Save CPSR
350 str r0, [r8, #8] @ Save OLD_R0
354 .macro irq_restore_user_regs
355 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
357 ldr lr, [sp, #S_PC] @ Get PC
358 add sp, sp, #S_FRAME_SIZE
359 subs pc, lr, #4 @ return & move spsr_svc into
364 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
367 str lr, [r13] @ save caller lr in position 0
369 mrs lr, spsr @ get the spsr
370 str lr, [r13, #4] @ save spsr in position 1 of
373 mov r13, #MODE_SVC @ prepare SVC-Mode
375 msr spsr, r13 @ switch modes, make sure
377 mov lr, pc @ capture return pc
378 movs pc, lr @ jump to next instruction &
382 .macro get_bad_stack_swi
383 sub r13, r13, #4 @ space on current stack for
385 str r0, [r13] @ save R0's value.
386 ldr r0, IRQ_STACK_START_IN @ get data regions start
387 @ spots for abort stack
388 str lr, [r0] @ save caller lr in position 0
390 mrs lr, spsr @ get the spsr
391 str lr, [r0, #4] @ save spsr in position 1 of
393 ldr lr, [r0] @ restore lr
394 ldr r0, [r13] @ restore r0
395 add r13, r13, #4 @ pop stack entry
398 .macro get_irq_stack @ setup IRQ stack
399 ldr sp, IRQ_STACK_START
402 .macro get_fiq_stack @ setup FIQ stack
403 ldr sp, FIQ_STACK_START
410 undefined_instruction:
413 bl do_undefined_instruction
419 bl do_software_interrupt
439 #ifdef CONFIG_USE_IRQ
446 irq_restore_user_regs
451 /* someone ought to write a more effective fiq_save_user_regs */
454 irq_restore_user_regs
470 #endif /* CONFIG_USE_IRQ */
471 #endif /* CONFIG_SPL_BUILD */