2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 ldr pc, _undefined_instruction
38 ldr pc, _software_interrupt
39 ldr pc, _prefetch_abort
45 _undefined_instruction: .word undefined_instruction
46 _software_interrupt: .word software_interrupt
47 _prefetch_abort: .word prefetch_abort
48 _data_abort: .word data_abort
49 _not_used: .word not_used
52 _pad: .word 0x12345678 /* now 16*4=64 */
56 .balignl 16,0xdeadbeef
57 /*************************************************************************
59 * Startup Code (reset vector)
61 * do important init only if we don't start from memory!
62 * setup Memory and board specific bits prior to relocation.
63 * relocate armboot to ram
66 *************************************************************************/
70 .word CONFIG_SYS_TEXT_BASE
72 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
79 * These are defined in the board-specific linker script.
83 .word __bss_start - _start
90 /* IRQ stack memory (calculated at run-time) */
91 .globl IRQ_STACK_START
95 /* IRQ stack memory (calculated at run-time) */
96 .globl FIQ_STACK_START
101 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
102 /* IRQ stack memory (calculated at run-time) + 8 bytes */
103 .globl IRQ_STACK_START_IN
107 .globl _datarel_start_ofs
109 .word __datarel_start - _start
111 .globl _datarelrolocal_start_ofs
112 _datarelrolocal_start_ofs:
113 .word __datarelrolocal_start - _start
115 .globl _datarellocal_start_ofs
116 _datarellocal_start_ofs:
117 .word __datarellocal_start - _start
119 .globl _datarelro_start_ofs
120 _datarelro_start_ofs:
121 .word __datarelro_start - _start
123 .globl _got_start_ofs
125 .word __got_start - _start
129 .word __got_end - _start
132 * the actual reset code
137 * set the cpu to SVC32 mode
144 #if (CONFIG_OMAP34XX)
145 /* Copy vectors to mask ROM indirect addr */
146 adr r0, _start @ r0 <- current position of code
147 add r0, r0, #4 @ skip reset vector
148 mov r2, #64 @ r2 <- size to copy
149 add r2, r0, r2 @ r2 <- source end address
150 mov r1, #SRAM_OFFSET0 @ build vect addr
151 mov r3, #SRAM_OFFSET1
153 mov r3, #SRAM_OFFSET2
156 ldmia r0!, {r3 - r10} @ copy from source address [r0]
157 stmia r1!, {r3 - r10} @ copy to target address [r1]
158 cmp r0, r2 @ until source end address [r2]
159 bne next @ loop until equal */
160 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
161 /* No need to copy/exec the clock code - DPLL adjust already done
162 * in NAND/oneNAND Boot.
164 bl cpy_clk_code @ put dpll adjust code behind vectors
165 #endif /* NAND Boot */
167 /* the mask ROM code should have PLL and others stable */
168 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
172 /* Set stackpointer in internal RAM to call board_init_f */
174 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
178 /*------------------------------------------------------------------------------*/
181 * void relocate_code (addr_sp, gd, addr_moni)
183 * This "function" does not return, instead it continues in RAM
184 * after relocating the monitor code.
189 mov r4, r0 /* save addr_sp */
190 mov r5, r1 /* save addr of gd */
191 mov r6, r2 /* save addr of destination */
192 mov r7, r2 /* save addr of destination */
194 /* Set up the stack */
198 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
201 ldr r3, _bss_start_ofs
202 add r2, r0, r3 /* r2 <- source end address */
204 #ifndef CONFIG_PRELOADER
209 ldmia r0!, {r9-r10} /* copy from source address [r0] */
210 stmia r6!, {r9-r10} /* copy to target address [r1] */
211 cmp r0, r2 /* until source end address [r2] */
214 #ifndef CONFIG_PRELOADER
216 * fix .rel.dyn relocations
218 ldr r0, _TEXT_BASE /* r0 <- Text base */
219 sub r9, r7, r0 /* r9 <- relocation offset */
220 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
221 add r10, r10, r0 /* r10 <- sym table in FLASH */
222 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
223 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
224 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
225 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
227 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
228 add r0, r0, r9 /* r0 <- location to fix up in RAM */
231 cmp r8, #23 /* relative fixup? */
233 cmp r8, #2 /* absolute fixup? */
235 /* ignore unknown type of fixup */
238 /* absolute fix: set location to (offset) symbol value */
239 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
240 add r1, r10, r1 /* r1 <- address of symbol in table */
241 ldr r1, [r1, #4] /* r1 <- symbol value */
242 add r1, r9 /* r1 <- relocated sym addr */
245 /* relative fix: increase location by offset */
250 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
255 ldr r0, _bss_start_ofs
257 ldr r3, _TEXT_BASE /* Text base */
258 mov r4, r7 /* reloc addr */
261 mov r2, #0x00000000 /* clear */
263 clbss_l:str r2, [r0] /* clear loop... */
267 #endif /* #ifndef CONFIG_PRELOADER */
268 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
271 * We are done. Do not return, instead branch to second part of board
272 * initialization, now running from RAM.
275 ldr r0, _board_init_r_ofs
279 /* setup parameters for board_init_r */
280 mov r0, r5 /* gd_t */
281 mov r1, r7 /* dest_addr */
286 .word board_init_r - _start
289 .word __rel_dyn_start - _start
291 .word __rel_dyn_end - _start
293 .word __dynsym_start - _start
295 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
297 * the actual reset code
302 * set the cpu to SVC32 mode
309 #if (CONFIG_OMAP34XX)
310 /* Copy vectors to mask ROM indirect addr */
311 adr r0, _start @ r0 <- current position of code
312 add r0, r0, #4 @ skip reset vector
313 mov r2, #64 @ r2 <- size to copy
314 add r2, r0, r2 @ r2 <- source end address
315 mov r1, #SRAM_OFFSET0 @ build vect addr
316 mov r3, #SRAM_OFFSET1
318 mov r3, #SRAM_OFFSET2
321 ldmia r0!, {r3 - r10} @ copy from source address [r0]
322 stmia r1!, {r3 - r10} @ copy to target address [r1]
323 cmp r0, r2 @ until source end address [r2]
324 bne next @ loop until equal */
325 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
326 /* No need to copy/exec the clock code - DPLL adjust already done
327 * in NAND/oneNAND Boot.
329 bl cpy_clk_code @ put dpll adjust code behind vectors
330 #endif /* NAND Boot */
332 /* the mask ROM code should have PLL and others stable */
333 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
337 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
338 relocate: @ relocate U-Boot to RAM
339 adr r0, _start @ r0 <- current position of code
340 ldr r1, _TEXT_BASE @ test if we run from flash or RAM
341 cmp r0, r1 @ don't reloc during debug
344 ldr r2, _armboot_start
346 sub r2, r3, r2 @ r2 <- size of armboot
347 add r2, r0, r2 @ r2 <- source end address
349 copy_loop: @ copy 32 bytes at a time
350 ldmia r0!, {r3 - r10} @ copy from source address [r0]
351 stmia r1!, {r3 - r10} @ copy to target address [r1]
352 cmp r0, r2 @ until source end address [r2]
354 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
356 /* Set up the stack */
358 ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
359 sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
360 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
361 #ifdef CONFIG_USE_IRQ
362 sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
364 sub sp, r0, #12 @ leave 3 words for abort-stack
365 bic sp, sp, #7 @ 8-byte alignment for ABI compliance
367 /* Clear BSS (if any). Is below tx (watch load addr - need space) */
369 ldr r0, _bss_start @ find start of bss segment
370 ldr r1, _bss_end @ stop here
371 mov r2, #0x00000000 @ clear value
373 str r2, [r0] @ clear BSS location
374 cmp r0, r1 @ are we at the end yet
375 add r0, r0, #4 @ increment clear index pointer
376 bne clbss_l @ keep clearing till at end
378 ldr pc, _start_armboot @ jump to C code
380 _start_armboot: .word start_armboot
381 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
383 /*************************************************************************
385 * CPU_init_critical registers
387 * setup important registers
388 * setup memory timing
390 *************************************************************************/
395 mov r0, #0 @ set up for MCR
396 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
397 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
400 * disable MMU stuff and caches
402 mrc p15, 0, r0, c1, c0, 0
403 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
404 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
405 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
406 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
407 mcr p15, 0, r0, c1, c0, 0
410 * Jump to board specific initialization...
411 * The Mask ROM will have already initialized
412 * basic memory. Go here to bump up clock rate and handle
413 * wake up conditions.
415 mov ip, lr @ persevere link reg across call
416 bl lowlevel_init @ go setup pll,mux,memory
417 mov lr, ip @ restore link
418 mov pc, lr @ back to my caller
420 *************************************************************************
424 *************************************************************************
429 #define S_FRAME_SIZE 72
451 #define MODE_SVC 0x13
455 * use bad_save_user_regs for abort/prefetch/undef/swi ...
456 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
459 .macro bad_save_user_regs
460 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
462 stmia sp, {r0 - r12} @ Save user registers (now in
464 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
465 ldr r2, _armboot_start
466 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
467 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
469 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
472 ldmia r2, {r2 - r3} @ get values for "aborted" pc
473 @ and cpsr (into parm regs)
474 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
478 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
479 mov r0, sp @ save current stack into r0
483 .macro irq_save_user_regs
484 sub sp, sp, #S_FRAME_SIZE
485 stmia sp, {r0 - r12} @ Calling r0-r12
486 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
487 @ a reserved stack spot would
489 stmdb r8, {sp, lr}^ @ Calling SP, LR
490 str lr, [r8, #0] @ Save calling PC
492 str r6, [r8, #4] @ Save CPSR
493 str r0, [r8, #8] @ Save OLD_R0
497 .macro irq_restore_user_regs
498 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
500 ldr lr, [sp, #S_PC] @ Get PC
501 add sp, sp, #S_FRAME_SIZE
502 subs pc, lr, #4 @ return & move spsr_svc into
507 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
508 ldr r13, _armboot_start @ setup our mode stack (enter
509 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
510 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
512 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
516 str lr, [r13] @ save caller lr in position 0
518 mrs lr, spsr @ get the spsr
519 str lr, [r13, #4] @ save spsr in position 1 of
522 mov r13, #MODE_SVC @ prepare SVC-Mode
524 msr spsr, r13 @ switch modes, make sure
526 mov lr, pc @ capture return pc
527 movs pc, lr @ jump to next instruction &
531 .macro get_bad_stack_swi
532 sub r13, r13, #4 @ space on current stack for
534 str r0, [r13] @ save R0's value.
535 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
536 ldr r0, _armboot_start @ get data regions start
537 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
538 sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
540 ldr r0, IRQ_STACK_START_IN @ get data regions start
541 @ spots for abort stack
543 str lr, [r0] @ save caller lr in position 0
545 mrs r0, spsr @ get the spsr
546 str lr, [r0, #4] @ save spsr in position 1 of
548 ldr r0, [r13] @ restore r0
549 add r13, r13, #4 @ pop stack entry
552 .macro get_irq_stack @ setup IRQ stack
553 ldr sp, IRQ_STACK_START
556 .macro get_fiq_stack @ setup FIQ stack
557 ldr sp, FIQ_STACK_START
564 undefined_instruction:
567 bl do_undefined_instruction
573 bl do_software_interrupt
593 #ifdef CONFIG_USE_IRQ
600 irq_restore_user_regs
605 /* someone ought to write a more effective fiq_save_user_regs */
608 irq_restore_user_regs