2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 ldr pc, _undefined_instruction
38 ldr pc, _software_interrupt
39 ldr pc, _prefetch_abort
45 _undefined_instruction: .word undefined_instruction
46 _software_interrupt: .word software_interrupt
47 _prefetch_abort: .word prefetch_abort
48 _data_abort: .word data_abort
49 _not_used: .word not_used
52 _pad: .word 0x12345678 /* now 16*4=64 */
56 .balignl 16,0xdeadbeef
57 /*************************************************************************
59 * Startup Code (reset vector)
61 * do important init only if we don't start from memory!
62 * setup Memory and board specific bits prior to relocation.
63 * relocate armboot to ram
66 *************************************************************************/
72 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
79 * These are defined in the board-specific linker script.
90 /* IRQ stack memory (calculated at run-time) */
91 .globl IRQ_STACK_START
95 /* IRQ stack memory (calculated at run-time) */
96 .globl FIQ_STACK_START
101 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
102 /* IRQ stack memory (calculated at run-time) + 8 bytes */
103 .globl IRQ_STACK_START_IN
107 .globl _datarel_start
109 .word __datarel_start
111 .globl _datarelrolocal_start
112 _datarelrolocal_start:
113 .word __datarelrolocal_start
115 .globl _datarellocal_start
117 .word __datarellocal_start
119 .globl _datarelro_start
121 .word __datarelro_start
132 * the actual reset code
137 * set the cpu to SVC32 mode
144 #if (CONFIG_OMAP34XX)
145 /* Copy vectors to mask ROM indirect addr */
146 adr r0, _start @ r0 <- current position of code
147 add r0, r0, #4 @ skip reset vector
148 mov r2, #64 @ r2 <- size to copy
149 add r2, r0, r2 @ r2 <- source end address
150 mov r1, #SRAM_OFFSET0 @ build vect addr
151 mov r3, #SRAM_OFFSET1
153 mov r3, #SRAM_OFFSET2
156 ldmia r0!, {r3 - r10} @ copy from source address [r0]
157 stmia r1!, {r3 - r10} @ copy to target address [r1]
158 cmp r0, r2 @ until source end address [r2]
159 bne next @ loop until equal */
160 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
161 /* No need to copy/exec the clock code - DPLL adjust already done
162 * in NAND/oneNAND Boot.
164 bl cpy_clk_code @ put dpll adjust code behind vectors
165 #endif /* NAND Boot */
167 /* the mask ROM code should have PLL and others stable */
168 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
172 /* Set stackpointer in internal RAM to call board_init_f */
174 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
178 /*------------------------------------------------------------------------------*/
181 * void relocate_code (addr_sp, gd, addr_moni)
183 * This "function" does not return, instead it continues in RAM
184 * after relocating the monitor code.
189 mov r4, r0 /* save addr_sp */
190 mov r5, r1 /* save addr of gd */
191 mov r6, r2 /* save addr of destination */
192 mov r7, r2 /* save addr of destination */
194 /* Set up the stack */
198 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
202 sub r2, r3, r2 /* r2 <- size of armboot */
203 add r2, r0, r2 /* r2 <- source end address */
205 #ifndef CONFIG_PRELOADER
210 ldmia r0!, {r9-r10} /* copy from source address [r0] */
211 stmia r6!, {r9-r10} /* copy to target address [r1] */
212 cmp r0, r2 /* until source end address [r2] */
215 #ifndef CONFIG_PRELOADER
216 /* fix got entries */
218 mov r0, r7 /* reloc addr */
219 ldr r2, _got_start /* addr in Flash */
220 ldr r3, _got_end /* addr in Flash */
238 ldr r3, _TEXT_BASE /* Text base */
239 mov r4, r7 /* reloc addr */
244 mov r2, #0x00000000 /* clear */
246 clbss_l:str r2, [r0] /* clear loop... */
250 #endif /* #ifndef CONFIG_PRELOADER */
251 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
254 * We are done. Do not return, instead branch to second part of board
255 * initialization, now running from RAM.
259 ldr r2, _board_init_r
261 add r2, r2, r7 /* position from board_init_r in RAM */
262 /* setup parameters for board_init_r */
263 mov r0, r5 /* gd_t */
264 mov r1, r7 /* dest_addr */
269 _board_init_r: .word board_init_r
270 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
272 * the actual reset code
277 * set the cpu to SVC32 mode
284 #if (CONFIG_OMAP34XX)
285 /* Copy vectors to mask ROM indirect addr */
286 adr r0, _start @ r0 <- current position of code
287 add r0, r0, #4 @ skip reset vector
288 mov r2, #64 @ r2 <- size to copy
289 add r2, r0, r2 @ r2 <- source end address
290 mov r1, #SRAM_OFFSET0 @ build vect addr
291 mov r3, #SRAM_OFFSET1
293 mov r3, #SRAM_OFFSET2
296 ldmia r0!, {r3 - r10} @ copy from source address [r0]
297 stmia r1!, {r3 - r10} @ copy to target address [r1]
298 cmp r0, r2 @ until source end address [r2]
299 bne next @ loop until equal */
300 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
301 /* No need to copy/exec the clock code - DPLL adjust already done
302 * in NAND/oneNAND Boot.
304 bl cpy_clk_code @ put dpll adjust code behind vectors
305 #endif /* NAND Boot */
307 /* the mask ROM code should have PLL and others stable */
308 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
312 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
313 relocate: @ relocate U-Boot to RAM
314 adr r0, _start @ r0 <- current position of code
315 ldr r1, _TEXT_BASE @ test if we run from flash or RAM
316 cmp r0, r1 @ don't reloc during debug
319 ldr r2, _armboot_start
321 sub r2, r3, r2 @ r2 <- size of armboot
322 add r2, r0, r2 @ r2 <- source end address
324 copy_loop: @ copy 32 bytes at a time
325 ldmia r0!, {r3 - r10} @ copy from source address [r0]
326 stmia r1!, {r3 - r10} @ copy to target address [r1]
327 cmp r0, r2 @ until source end address [r2]
329 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
331 /* Set up the stack */
333 ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
334 sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
335 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
336 #ifdef CONFIG_USE_IRQ
337 sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
339 sub sp, r0, #12 @ leave 3 words for abort-stack
340 bic sp, sp, #7 @ 8-byte alignment for ABI compliance
342 /* Clear BSS (if any). Is below tx (watch load addr - need space) */
344 ldr r0, _bss_start @ find start of bss segment
345 ldr r1, _bss_end @ stop here
346 mov r2, #0x00000000 @ clear value
348 str r2, [r0] @ clear BSS location
349 cmp r0, r1 @ are we at the end yet
350 add r0, r0, #4 @ increment clear index pointer
351 bne clbss_l @ keep clearing till at end
353 ldr pc, _start_armboot @ jump to C code
355 _start_armboot: .word start_armboot
356 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
358 /*************************************************************************
360 * CPU_init_critical registers
362 * setup important registers
363 * setup memory timing
365 *************************************************************************/
370 mov r0, #0 @ set up for MCR
371 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
372 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
375 * disable MMU stuff and caches
377 mrc p15, 0, r0, c1, c0, 0
378 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
379 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
380 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
381 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
382 mcr p15, 0, r0, c1, c0, 0
385 * Jump to board specific initialization...
386 * The Mask ROM will have already initialized
387 * basic memory. Go here to bump up clock rate and handle
388 * wake up conditions.
390 mov ip, lr @ persevere link reg across call
391 bl lowlevel_init @ go setup pll,mux,memory
392 mov lr, ip @ restore link
393 mov pc, lr @ back to my caller
395 *************************************************************************
399 *************************************************************************
404 #define S_FRAME_SIZE 72
426 #define MODE_SVC 0x13
430 * use bad_save_user_regs for abort/prefetch/undef/swi ...
431 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
434 .macro bad_save_user_regs
435 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
437 stmia sp, {r0 - r12} @ Save user registers (now in
439 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
440 ldr r2, _armboot_start
441 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
442 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
444 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
447 ldmia r2, {r2 - r3} @ get values for "aborted" pc
448 @ and cpsr (into parm regs)
449 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
453 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
454 mov r0, sp @ save current stack into r0
458 .macro irq_save_user_regs
459 sub sp, sp, #S_FRAME_SIZE
460 stmia sp, {r0 - r12} @ Calling r0-r12
461 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
462 @ a reserved stack spot would
464 stmdb r8, {sp, lr}^ @ Calling SP, LR
465 str lr, [r8, #0] @ Save calling PC
467 str r6, [r8, #4] @ Save CPSR
468 str r0, [r8, #8] @ Save OLD_R0
472 .macro irq_restore_user_regs
473 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
475 ldr lr, [sp, #S_PC] @ Get PC
476 add sp, sp, #S_FRAME_SIZE
477 subs pc, lr, #4 @ return & move spsr_svc into
482 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
483 ldr r13, _armboot_start @ setup our mode stack (enter
484 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
485 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
487 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
491 str lr, [r13] @ save caller lr in position 0
493 mrs lr, spsr @ get the spsr
494 str lr, [r13, #4] @ save spsr in position 1 of
497 mov r13, #MODE_SVC @ prepare SVC-Mode
499 msr spsr, r13 @ switch modes, make sure
501 mov lr, pc @ capture return pc
502 movs pc, lr @ jump to next instruction &
506 .macro get_bad_stack_swi
507 sub r13, r13, #4 @ space on current stack for
509 str r0, [r13] @ save R0's value.
510 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
511 ldr r0, _armboot_start @ get data regions start
512 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
513 sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
515 ldr r0, IRQ_STACK_START_IN @ get data regions start
516 @ spots for abort stack
518 str lr, [r0] @ save caller lr in position 0
520 mrs r0, spsr @ get the spsr
521 str lr, [r0, #4] @ save spsr in position 1 of
523 ldr r0, [r13] @ restore r0
524 add r13, r13, #4 @ pop stack entry
527 .macro get_irq_stack @ setup IRQ stack
528 ldr sp, IRQ_STACK_START
531 .macro get_fiq_stack @ setup FIQ stack
532 ldr sp, FIQ_STACK_START
539 undefined_instruction:
542 bl do_undefined_instruction
548 bl do_software_interrupt
568 #ifdef CONFIG_USE_IRQ
575 irq_restore_user_regs
580 /* someone ought to write a more effective fiq_save_user_regs */
583 irq_restore_user_regs