2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
17 #ifdef CONFIG_SPL_BUILD
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/spl.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <asm/arch/tzpc.h>
28 #include <asm/arch/mmc.h>
30 #include <linux/compiler.h>
41 struct fel_stash fel_stash __attribute__((section(".data")));
43 static int gpio_init(void)
45 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
46 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
47 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
48 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
49 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
51 #if defined(CONFIG_MACH_SUN8I)
52 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
53 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
55 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
56 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
58 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
59 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
60 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
61 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
62 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
63 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
64 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
65 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
66 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
67 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
68 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
69 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
70 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
71 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
72 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
73 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
74 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
75 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
76 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
77 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
78 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
79 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
80 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
81 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
82 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
83 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
84 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
85 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
86 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
87 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
88 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
89 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
90 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
91 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
94 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
95 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
97 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
98 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
100 #error Unsupported console port number. Please fix pin mux settings in board.c
106 int spl_board_load_image(void)
108 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
109 return_to_fel(fel_stash.sp, fel_stash.lr);
117 * Undocumented magic taken from boot0, without this DRAM
118 * access gets messed up (seems cache related).
119 * The boot0 sources describe this as: "config ema for cache sram"
121 #if defined CONFIG_MACH_SUN6I
122 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
123 #elif defined CONFIG_MACH_SUN8I
124 __maybe_unused uint version;
126 /* Unlock sram version info reg, read it, relock */
127 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
128 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
129 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
132 * Ideally this would be a switch case, but we do not know exactly
133 * which versions there are and which version needs which settings,
134 * so reproduce the per SoC code from the BSP.
136 #if defined CONFIG_MACH_SUN8I_A23
137 if (version == 0x1650)
138 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
140 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
141 #elif defined CONFIG_MACH_SUN8I_A33
142 if (version != 0x1667)
143 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
145 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
146 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
149 #if defined CONFIG_MACH_SUN6I || \
150 defined CONFIG_MACH_SUN7I || \
151 defined CONFIG_MACH_SUN8I
152 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
154 "mrc p15, 0, r0, c1, c0, 1\n"
155 "orr r0, r0, #1 << 6\n"
156 "mcr p15, 0, r0, c1, c0, 1\n");
158 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
159 /* Enable non-secure access to some peripherals */
170 #ifdef CONFIG_SPL_BUILD
171 DECLARE_GLOBAL_DATA_PTR;
173 /* The sunxi internal brom will try to loader external bootloader
174 * from mmc0, nand flash, mmc2.
176 u32 spl_boot_device(void)
178 __maybe_unused struct mmc *mmc0, *mmc1;
180 * When booting from the SD card or NAND memory, the "eGON.BT0"
181 * signature is expected to be found in memory at the address 0x0004
182 * (see the "mksunxiboot" tool, which generates this header).
184 * When booting in the FEL mode over USB, this signature is patched in
185 * memory and replaced with something else by the 'fel' tool. This other
186 * signature is selected in such a way, that it can't be present in a
187 * valid bootable SD card image (because the BROM would refuse to
188 * execute the SPL in this case).
190 * This checks for the signature and if it is not found returns to
191 * the FEL code in the BROM to wait and receive the main u-boot
192 * binary over USB. If it is found, it determines where SPL was
195 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
196 return BOOT_DEVICE_BOARD;
198 /* The BROM will try to boot from mmc0 first, so try that first. */
200 mmc_initialize(gd->bd);
201 mmc0 = find_mmc_device(0);
202 if (sunxi_mmc_has_egon_boot_signature(mmc0))
203 return BOOT_DEVICE_MMC1;
206 /* Fallback to booting NAND if enabled. */
207 if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
208 return BOOT_DEVICE_NAND;
211 if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
212 mmc1 = find_mmc_device(1);
213 if (sunxi_mmc_has_egon_boot_signature(mmc1))
214 return BOOT_DEVICE_MMC2;
218 panic("Could not determine boot source\n");
219 return -1; /* Never reached */
222 /* No confirmation data available in SPL yet. Hardcode bootmode */
223 u32 spl_boot_mode(void)
225 return MMCSD_MODE_RAW;
228 void board_init_f(ulong dummy)
231 preloader_console_init();
233 #ifdef CONFIG_SPL_I2C_SUPPORT
234 /* Needed early by sunxi_board_init if PMU is enabled */
235 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
241 void reset_cpu(ulong addr)
243 #ifdef CONFIG_SUNXI_GEN_SUN4I
244 static const struct sunxi_wdog *wdog =
245 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
247 /* Set the watchdog for its shortest interval (.5s) and wait */
248 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
249 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
252 /* sun5i sometimes gets stuck without this */
253 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
256 #ifdef CONFIG_SUNXI_GEN_SUN6I
257 static const struct sunxi_wdog *wdog =
258 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
260 /* Set the watchdog for its shortest interval (.5s) and wait */
261 writel(WDT_CFG_RESET, &wdog->cfg);
262 writel(WDT_MODE_EN, &wdog->mode);
263 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
268 #ifndef CONFIG_SYS_DCACHE_OFF
269 void enable_caches(void)
271 /* Enable D-cache. I-cache is already enabled in start.S */