2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
17 #ifdef CONFIG_SPL_BUILD
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/spl.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <asm/arch/tzpc.h>
28 #include <asm/arch/mmc.h>
30 #include <linux/compiler.h>
41 struct fel_stash fel_stash __attribute__((section(".data")));
43 static int gpio_init(void)
45 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
46 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
47 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
48 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
49 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
51 #if defined(CONFIG_MACH_SUN8I)
52 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
53 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
55 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
56 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
58 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
59 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
60 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
61 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
62 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
63 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
64 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
65 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
66 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
67 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
68 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
69 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
70 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
71 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
72 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
73 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
74 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
75 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
76 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
77 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
78 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
79 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
80 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
81 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
82 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
83 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
84 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
85 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
86 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
87 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
88 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
89 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
90 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
92 #error Unsupported console port number. Please fix pin mux settings in board.c
98 void spl_board_load_image(void)
100 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
101 return_to_fel(fel_stash.sp, fel_stash.lr);
106 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
107 /* Magic (undocmented) value taken from boot0, without this DRAM
108 * access gets messed up (seems cache related) */
109 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
111 #if defined CONFIG_MACH_SUN6I || \
112 defined CONFIG_MACH_SUN7I || \
113 defined CONFIG_MACH_SUN8I
114 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
116 "mrc p15, 0, r0, c1, c0, 1\n"
117 "orr r0, r0, #1 << 6\n"
118 "mcr p15, 0, r0, c1, c0, 1\n");
120 #if defined CONFIG_MACH_SUN6I
121 /* Enable non-secure access to the RTC */
131 #ifdef CONFIG_SPL_BUILD
132 DECLARE_GLOBAL_DATA_PTR;
134 /* The sunxi internal brom will try to loader external bootloader
135 * from mmc0, nand flash, mmc2.
137 u32 spl_boot_device(void)
139 struct mmc *mmc0, *mmc1;
141 * When booting from the SD card or NAND memory, the "eGON.BT0"
142 * signature is expected to be found in memory at the address 0x0004
143 * (see the "mksunxiboot" tool, which generates this header).
145 * When booting in the FEL mode over USB, this signature is patched in
146 * memory and replaced with something else by the 'fel' tool. This other
147 * signature is selected in such a way, that it can't be present in a
148 * valid bootable SD card image (because the BROM would refuse to
149 * execute the SPL in this case).
151 * This checks for the signature and if it is not found returns to
152 * the FEL code in the BROM to wait and receive the main u-boot
153 * binary over USB. If it is found, it determines where SPL was
156 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
157 return BOOT_DEVICE_BOARD;
159 /* The BROM will try to boot from mmc0 first, so try that first. */
160 mmc_initialize(gd->bd);
161 mmc0 = find_mmc_device(0);
162 if (sunxi_mmc_has_egon_boot_signature(mmc0))
163 return BOOT_DEVICE_MMC1;
165 /* Fallback to booting NAND if enabled. */
166 if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
167 return BOOT_DEVICE_NAND;
169 if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
170 mmc1 = find_mmc_device(1);
171 if (sunxi_mmc_has_egon_boot_signature(mmc1)) {
173 * spl_mmc.c: spl_mmc_load_image() is hard-coded to
174 * use find_mmc_device(0), no matter what we
175 * return. Swap mmc0 and mmc2 to make this work.
177 mmc0->block_dev.dev = 1;
178 mmc1->block_dev.dev = 0;
179 return BOOT_DEVICE_MMC2;
183 panic("Could not determine boot source\n");
184 return -1; /* Never reached */
187 /* No confirmation data available in SPL yet. Hardcode bootmode */
188 u32 spl_boot_mode(void)
190 return MMCSD_MODE_RAW;
193 void board_init_f(ulong dummy)
195 preloader_console_init();
197 #ifdef CONFIG_SPL_I2C_SUPPORT
198 /* Needed early by sunxi_board_init if PMU is enabled */
199 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
205 void reset_cpu(ulong addr)
207 #ifdef CONFIG_SUNXI_GEN_SUN4I
208 static const struct sunxi_wdog *wdog =
209 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
211 /* Set the watchdog for its shortest interval (.5s) and wait */
212 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
213 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
216 /* sun5i sometimes gets stuck without this */
217 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
220 #ifdef CONFIG_SUNXI_GEN_SUN6I
221 static const struct sunxi_wdog *wdog =
222 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
224 /* Set the watchdog for its shortest interval (.5s) and wait */
225 writel(WDT_CFG_RESET, &wdog->cfg);
226 writel(WDT_MODE_EN, &wdog->mode);
227 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
232 #ifndef CONFIG_SYS_DCACHE_OFF
233 void enable_caches(void)
235 /* Enable D-cache. I-cache is already enabled in start.S */
240 #ifdef CONFIG_CMD_NET
242 * Initializes on-chip ethernet controllers.
243 * to override, implement board_eth_init()
245 int cpu_eth_init(bd_t *bis)
247 __maybe_unused int rc;
250 gpio_request(CONFIG_MACPWR, "macpwr");
251 gpio_direction_output(CONFIG_MACPWR, 1);
255 #ifdef CONFIG_SUNXI_GMAC
256 rc = sunxi_gmac_initialize(bis);
258 printf("sunxi: failed to initialize gmac\n");