2 * sun4i, sun5i and sun7i specific clock code
4 * (C) Copyright 2007-2012
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/sys_proto.h>
19 #ifdef CONFIG_SPL_BUILD
20 void clock_init_safe(void)
22 struct sunxi_ccm_reg * const ccm =
23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25 /* Set safe defaults until PMU is configured */
26 writel(AXI_DIV_1 << AXI_DIV_SHIFT |
27 AHB_DIV_2 << AHB_DIV_SHIFT |
28 APB0_DIV_1 << APB0_DIV_SHIFT |
29 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
30 &ccm->cpu_ahb_apb0_cfg);
31 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
33 writel(AXI_DIV_1 << AXI_DIV_SHIFT |
34 AHB_DIV_2 << AHB_DIV_SHIFT |
35 APB0_DIV_1 << APB0_DIV_SHIFT |
36 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
37 &ccm->cpu_ahb_apb0_cfg);
38 #ifdef CONFIG_MACH_SUN7I
39 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
41 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
42 #ifdef CONFIG_SUNXI_AHCI
43 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
44 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
49 void clock_init_uart(void)
51 struct sunxi_ccm_reg *const ccm =
52 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
54 /* uart clock source is apb1 */
55 writel(APB1_CLK_SRC_OSC24M|
58 &ccm->apb1_clk_div_cfg);
60 /* open the clock for uart */
61 setbits_le32(&ccm->apb1_gate,
62 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
65 int clock_twi_onoff(int port, int state)
67 struct sunxi_ccm_reg *const ccm =
68 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
73 /* set the apb clock gate for twi */
75 setbits_le32(&ccm->apb1_gate,
76 CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
78 clrbits_le32(&ccm->apb1_gate,
79 CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
84 #ifdef CONFIG_SPL_BUILD
85 #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
86 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
87 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
88 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
89 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
90 (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
91 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
92 (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
93 (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
94 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
95 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
96 (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
102 /* This array must be ordered by frequency. */
103 { PLL1_CFG(31, 1, 0, 0), 1488000000},
104 { PLL1_CFG(30, 1, 0, 0), 1440000000},
105 { PLL1_CFG(29, 1, 0, 0), 1392000000},
106 { PLL1_CFG(28, 1, 0, 0), 1344000000},
107 { PLL1_CFG(27, 1, 0, 0), 1296000000},
108 { PLL1_CFG(26, 1, 0, 0), 1248000000},
109 { PLL1_CFG(25, 1, 0, 0), 1200000000},
110 { PLL1_CFG(24, 1, 0, 0), 1152000000},
111 { PLL1_CFG(23, 1, 0, 0), 1104000000},
112 { PLL1_CFG(22, 1, 0, 0), 1056000000},
113 { PLL1_CFG(21, 1, 0, 0), 1008000000},
114 { PLL1_CFG(20, 1, 0, 0), 960000000 },
115 { PLL1_CFG(19, 1, 0, 0), 912000000 },
116 { PLL1_CFG(16, 1, 0, 0), 768000000 },
117 /* Final catchall entry 384MHz*/
118 { PLL1_CFG(16, 0, 0, 0), 0 },
122 void clock_set_pll1(unsigned int hz)
126 struct sunxi_ccm_reg * const ccm =
127 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
129 /* Find target frequency */
130 while (pll1_para[i].freq > hz)
133 hz = pll1_para[i].freq;
137 /* Calculate system clock divisors */
138 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */
139 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */
140 apb0 = 2; /* Max 150MHz */
142 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
144 /* Map divisors to register values */
157 /* Switch to 24MHz clock while changing PLL1 */
158 writel(AXI_DIV_1 << AXI_DIV_SHIFT |
159 AHB_DIV_2 << AHB_DIV_SHIFT |
160 APB0_DIV_1 << APB0_DIV_SHIFT |
161 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
162 &ccm->cpu_ahb_apb0_cfg);
165 /* Configure sys clock divisors */
166 writel(axi << AXI_DIV_SHIFT |
167 ahb << AHB_DIV_SHIFT |
168 apb0 << APB0_DIV_SHIFT |
169 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
170 &ccm->cpu_ahb_apb0_cfg);
172 /* Configure PLL1 at the desired frequency */
173 writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
176 /* Switch CPU to PLL1 */
177 writel(axi << AXI_DIV_SHIFT |
178 ahb << AHB_DIV_SHIFT |
179 apb0 << APB0_DIV_SHIFT |
180 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
181 &ccm->cpu_ahb_apb0_cfg);
186 void clock_set_pll3(unsigned int clk)
188 struct sunxi_ccm_reg * const ccm =
189 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
192 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
196 /* PLL3 rate = 3000000 * m */
197 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
198 CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
201 unsigned int clock_get_pll3(void)
203 struct sunxi_ccm_reg *const ccm =
204 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
205 uint32_t rval = readl(&ccm->pll3_cfg);
206 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT);
210 unsigned int clock_get_pll5p(void)
212 struct sunxi_ccm_reg *const ccm =
213 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
214 uint32_t rval = readl(&ccm->pll5_cfg);
215 int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
216 int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
217 int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
218 return (24000000 * n * k) >> p;
221 unsigned int clock_get_pll6(void)
223 struct sunxi_ccm_reg *const ccm =
224 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
225 uint32_t rval = readl(&ccm->pll6_cfg);
226 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
227 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
228 return 24000000 * n * k / 2;
231 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
233 int pll = clock_get_pll5p();
236 while ((pll / div) > hz)
239 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
240 CCM_DE_CTRL_M(div), clk_cfg);