git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/sunxi/clock_sun6i.c

   1 /*
   2  * sun6i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24         struct sunxi_prcm_reg * const prcm =
  25                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  26
  27         /* Set PLL ldo voltage without this PLL6 does not work properly */
  28         clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  29                         PRCM_PLL_CTRL_LDO_KEY);
  30         clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  31                 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  32                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  33         clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  34
  35         clock_set_pll1(408000000);
  36
  37         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  38         while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
  39                 ;
  40
  41         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  42
  43         writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
  44         writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
  45 }
  46 #endif
  47
  48 void clock_init_uart(void)
  49 {
  50 #if CONFIG_CONS_INDEX < 5
  51         struct sunxi_ccm_reg *const ccm =
  52                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  53
  54         /* uart clock source is apb2 */
  55         writel(APB2_CLK_SRC_OSC24M|
  56                APB2_CLK_RATE_N_1|
  57                APB2_CLK_RATE_M(1),
  58                &ccm->apb2_div);
  59
  60         /* open the clock for uart */
  61         setbits_le32(&ccm->apb2_gate,
  62                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  63                                        CONFIG_CONS_INDEX - 1));
  64
  65         /* deassert uart reset */
  66         setbits_le32(&ccm->apb2_reset_cfg,
  67                      1 << (APB2_RESET_UART_SHIFT +
  68                            CONFIG_CONS_INDEX - 1));
  69 #else
  70         /* enable R_PIO and R_UART clocks, and de-assert resets */
  71         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
  72 #endif
  73 }
  74
  75 int clock_twi_onoff(int port, int state)
  76 {
  77         struct sunxi_ccm_reg *const ccm =
  78                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  79
  80         /* set the apb clock gate for twi */
  81         if (state)
  82                 setbits_le32(&ccm->apb2_gate,
  83                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
  84         else
  85                 clrbits_le32(&ccm->apb2_gate,
  86                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
  87
  88         return 0;
  89 }
  90
  91 #ifdef CONFIG_SPL_BUILD
  92 void clock_set_pll1(unsigned int clk)
  93 {
  94         struct sunxi_ccm_reg * const ccm =
  95                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  96         const int p = 0;
  97         int k = 1;
  98         int m = 1;
  99
 100         if (clk > 1152000000) {
 101                 k = 2;
 102         } else if (clk > 768000000) {
 103                 k = 3;
 104                 m = 2;
 105         }
 106
 107         /* Switch to 24MHz clock while changing PLL1 */
 108         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 109                ATB_DIV_2 << ATB_DIV_SHIFT |
 110                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 111                &ccm->cpu_axi_cfg);
 112
 113         /*
 114          * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
 115          * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
 116          */
 117         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
 118                CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 119                CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
 120         sdelay(200);
 121
 122         /* Switch CPU to PLL1 */
 123         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 124                ATB_DIV_2 << ATB_DIV_SHIFT |
 125                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 126                &ccm->cpu_axi_cfg);
 127 }
 128 #endif
 129
 130 void clock_set_pll3(unsigned int clk)
 131 {
 132         struct sunxi_ccm_reg * const ccm =
 133                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 134         const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
 135
 136         if (clk == 0) {
 137                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 138                 return;
 139         }
 140
 141         /* PLL3 rate = 24000000 * n / m */
 142         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 143                CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
 144                &ccm->pll3_cfg);
 145 }
 146
 147 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 148 {
 149         struct sunxi_ccm_reg * const ccm =
 150                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 151         const int max_n = 32;
 152         int k = 1, m = 2;
 153
 154         if (sigma_delta_enable)
 155                 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 156
 157         /* PLL5 rate = 24000000 * n * k / m */
 158         if (clk > 24000000 * k * max_n / m) {
 159                 m = 1;
 160                 if (clk > 24000000 * k * max_n / m)
 161                         k = 2;
 162         }
 163         writel(CCM_PLL5_CTRL_EN |
 164                (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
 165                CCM_PLL5_CTRL_UPD |
 166                CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
 167                CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 168
 169         udelay(5500);
 170 }
 171
 172 #ifdef CONFIG_MACH_SUN6I
 173 void clock_set_mipi_pll(unsigned int clk)
 174 {
 175         struct sunxi_ccm_reg * const ccm =
 176                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 177         unsigned int k, m, n, value, diff;
 178         unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
 179         unsigned int src = clock_get_pll3();
 180
 181         /* All calculations are in KHz to avoid overflows */
 182         clk /= 1000;
 183         src /= 1000;
 184
 185         /* Pick the closest lower clock */
 186         for (k = 1; k <= 4; k++) {
 187                 for (m = 1; m <= 16; m++) {
 188                         for (n = 1; n <= 16; n++) {
 189                                 value = src * n * k / m;
 190                                 if (value > clk)
 191                                         continue;
 192
 193                                 diff = clk - value;
 194                                 if (diff < best_diff) {
 195                                         best_diff = diff;
 196                                         best_k = k;
 197                                         best_m = m;
 198                                         best_n = n;
 199                                 }
 200                                 if (diff == 0)
 201                                         goto done;
 202                         }
 203                 }
 204         }
 205
 206 done:
 207         writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
 208                CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
 209                CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_MACH_SUN8I_A33
 214 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 215 {
 216         struct sunxi_ccm_reg * const ccm =
 217                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 218
 219         if (sigma_delta_enable)
 220                 writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
 221
 222         writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
 223                (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
 224                CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
 225
 226         while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
 227                 ;
 228 }
 229 #endif
 230
 231 unsigned int clock_get_pll3(void)
 232 {
 233         struct sunxi_ccm_reg *const ccm =
 234                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 235         uint32_t rval = readl(&ccm->pll3_cfg);
 236         int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
 237         int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
 238
 239         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 240         return (24000 * n / m) * 1000;
 241 }
 242
 243 unsigned int clock_get_pll6(void)
 244 {
 245         struct sunxi_ccm_reg *const ccm =
 246                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 247         uint32_t rval = readl(&ccm->pll6_cfg);
 248         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
 249         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 250         return 24000000 * n * k / 2;
 251 }
 252
 253 unsigned int clock_get_mipi_pll(void)
 254 {
 255         struct sunxi_ccm_reg *const ccm =
 256                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 257         uint32_t rval = readl(&ccm->mipi_pll_cfg);
 258         unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
 259         unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
 260         unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
 261         unsigned int src = clock_get_pll3();
 262
 263         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 264         return ((src / 1000) * n * k / m) * 1000;
 265 }
 266
 267 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 268 {
 269         int pll = clock_get_pll6() * 2;
 270         int div = 1;
 271
 272         while ((pll / div) > hz)
 273                 div++;
 274
 275         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
 276                clk_cfg);
 277 }