2 * Copyright (C) 2015 - Chen-Yu Tsai
3 * Author: Chen-Yu Tsai <wens@csie.org>
5 * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <asm/arch-armv7/generictimer.h>
24 #include <asm/macro.h>
26 #include <asm/arch/cpu.h>
31 * SECURE_RAM to text_end :
32 * ._secure_text section
33 * text_end to ALIGN_PAGE(text_end):
35 * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
36 * 1kB of stack per CPU (4 CPUs max).
39 .pushsection ._secure.text, "ax"
43 #define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
44 #define TEN_MS (10 * ONE_MS)
45 #define GICD_BASE 0x1c81000
46 #define GICC_BASE 0x1c82000
53 mrc p15, 0, r7, c1, c1, 0
55 mcr p15, 0, r8, c1, c1, 0
58 @ Validate reason based on IAR and acknowledge
59 movw r8, #(GICC_BASE & 0xffff)
60 movt r8, #(GICC_BASE >> 16)
61 ldr r9, [r8, #GICC_IAR]
64 cmp r9, r10 @ skip spurious interrupt 1023
66 movw r10, #0x3fe @ ...and 1022
69 str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt
76 movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
77 movt r8, #(SUN6I_CPUCFG_BASE >> 16)
79 @ Wait for the core to enter WFI
83 1: ldr r10, [r11, #0x48]
86 timer_wait r10, ONE_MS
95 lsl r11, r10, r9 @ r11 is now CPU mask
100 movw r8, #(SUNXI_PRCM_BASE & 0xffff)
101 movt r8, #(SUNXI_PRCM_BASE >> 16)
104 ldr r10, [r8, #0x100]
106 str r10, [r8, #0x100]
107 timer_wait r10, ONE_MS
109 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
110 @ Activate power clamp
114 str r10, [r12, #0x140]
117 movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
118 movt r8, #(SUN6I_CPUCFG_BASE >> 16)
121 ldr r10, [r8, #0x1e4]
123 str r10, [r8, #0x1e4]
125 @ Restore security level
126 out: mcr p15, 0, r7, c1, c1, 0
138 bl psci_get_cpu_stack_top @ get stack top of target CPU
139 str r2, [r0] @ store target PC at stack top
142 movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
143 movt r0, #(SUN6I_CPUCFG_BASE >> 16)
146 and r1, r1, #3 @ only care about first cluster
150 ldr r6, =psci_cpu_entry
151 str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
153 @ Assert reset on target CPU
155 lsl r5, r1, #6 @ 64 bytes per CPU
156 add r5, r5, #0x40 @ Offset from base
157 add r5, r5, r0 @ CPU control block
158 str r6, [r5] @ Reset CPU
161 ldr r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
165 @ Lock CPU (Disable external debug access)
166 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
170 movw r0, #(SUNXI_PRCM_BASE & 0xffff)
171 movt r0, #(SUNXI_PRCM_BASE >> 16)
173 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
174 @ Release power clamp
175 lsl r5, r1, #2 @ 1 register per CPU
176 add r5, r5, r0 @ PRCM
180 str r6, [r5, #0x140] @ CPUx_PWR_CLAMP
184 timer_wait r6, TEN_MS
187 ldr r6, [r0, #0x100] @ CPU_PWROFF_GATING
191 @ re-calculate CPU control register address
192 movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
193 movt r0, #(SUN6I_CPUCFG_BASE >> 16)
195 @ Deassert reset on target CPU
197 lsl r5, r1, #6 @ 64 bytes per CPU
198 add r5, r5, #0x40 @ Offset from base
199 add r5, r5, r0 @ CPU control block
202 @ Unlock CPU (Enable external debug access)
203 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
207 mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
212 bl psci_cpu_off_common
214 @ Ask CPU0 to pull the rug...
215 movw r0, #(GICD_BASE & 0xffff)
216 movt r0, #(GICD_BASE >> 16)
218 movt r1, #1 @ Target is CPU0
219 str r1, [r0, #GICD_SGIR]
225 .globl psci_arch_init
229 movw r4, #(GICD_BASE & 0xffff)
230 movt r4, #(GICD_BASE >> 16)
232 ldr r5, [r4, #GICD_IGROUPRn]
233 bic r5, r5, #(1 << 15) @ SGI15 as Group-0
234 str r5, [r4, #GICD_IGROUPRn]
236 mov r5, #0 @ Set SGI15 priority to 0
237 strb r5, [r4, #(GICD_IPRIORITYRn + 15)]
239 add r4, r4, #0x1000 @ GICC address
242 str r5, [r4, #GICC_PMR] @ Be cool with non-secure
244 ldr r5, [r4, #GICC_CTLR]
245 orr r5, r5, #(1 << 3) @ Switch FIQEn on
246 str r5, [r4, #GICC_CTLR]
248 mrc p15, 0, r5, c1, c1, 0 @ Read SCR
249 orr r5, r5, #4 @ Enable FIQ in monitor mode
250 bic r5, r5, #1 @ Secure mode
251 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
254 bl psci_get_cpu_id @ CPU ID => r0
255 bl psci_get_cpu_stack_top @ stack top => r0