2 * Copyright (C) 2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Based on code by Carl van Schaik <carl@ok-labs.com>.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <asm/arch-armv7/generictimer.h>
24 #include <asm/macro.h>
26 #include <asm/arch/cpu.h>
31 * SECURE_RAM to text_end :
32 * ._secure_text section
33 * text_end to ALIGN_PAGE(text_end):
35 * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
36 * 1kB of stack per CPU (4 CPUs max).
39 .pushsection ._secure.text, "ax"
43 #define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
44 #define TEN_MS (10 * ONE_MS)
45 #define GICD_BASE 0x1c81000
46 #define GICC_BASE 0x1c82000
53 mrc p15, 0, r7, c1, c1, 0
55 mcr p15, 0, r8, c1, c1, 0
58 @ Validate reason based on IAR and acknowledge
59 movw r8, #(GICC_BASE & 0xffff)
60 movt r8, #(GICC_BASE >> 16)
61 ldr r9, [r8, #GICC_IAR]
64 cmp r9, r10 @ skip spurious interrupt 1023
66 movw r10, #0x3fe @ ...and 1022
69 str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt
76 movw r8, #(SUN7I_CPUCFG_BASE & 0xffff)
77 movt r8, #(SUN7I_CPUCFG_BASE >> 16)
79 @ Wait for the core to enter WFI
83 1: ldr r10, [r11, #0x48]
86 timer_wait r10, ONE_MS
95 lsl r9, r10, r9 @ r9 is now CPU mask
101 ldr r10, [r8, #0x1b4]
103 str r10, [r8, #0x1b4]
104 timer_wait r10, ONE_MS
106 @ Activate power clamp
108 1: str r10, [r8, #0x1b0]
114 @ Restore security level
115 out: mcr p15, 0, r7, c1, c1, 0
127 bl psci_get_cpu_stack_top @ get stack top of target CPU
128 str r2, [r0] @ store target PC at stack top
131 movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
132 movt r0, #(SUN7I_CPUCFG_BASE >> 16)
135 and r1, r1, #3 @ only care about first cluster
139 ldr r6, =psci_cpu_entry
140 str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
142 @ Assert reset on target CPU
144 lsl r5, r1, #6 @ 64 bytes per CPU
145 add r5, r5, #0x40 @ Offset from base
146 add r5, r5, r0 @ CPU control block
147 str r6, [r5] @ Reset CPU
150 ldr r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
154 @ Lock CPU (Disable external debug access)
155 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
159 @ Release power clamp
163 str r6, [r0, #0x1b0] @ CPU1_PWR_CLAMP
166 timer_wait r1, TEN_MS
169 ldr r6, [r0, #0x1b4] @ CPU1_PWROFF_REG
173 @ Deassert reset on target CPU
177 @ Unlock CPU (Enable external debug access)
178 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
182 mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
187 bl psci_cpu_off_common
189 @ Ask CPU0 to pull the rug...
190 movw r0, #(GICD_BASE & 0xffff)
191 movt r0, #(GICD_BASE >> 16)
193 movt r1, #1 @ Target is CPU0
194 str r1, [r0, #GICD_SGIR]
200 .globl psci_arch_init
204 movw r4, #(GICD_BASE & 0xffff)
205 movt r4, #(GICD_BASE >> 16)
207 ldr r5, [r4, #GICD_IGROUPRn]
208 bic r5, r5, #(1 << 15) @ SGI15 as Group-0
209 str r5, [r4, #GICD_IGROUPRn]
211 mov r5, #0 @ Set SGI15 priority to 0
212 strb r5, [r4, #(GICD_IPRIORITYRn + 15)]
214 add r4, r4, #0x1000 @ GICC address
217 str r5, [r4, #GICC_PMR] @ Be cool with non-secure
219 ldr r5, [r4, #GICC_CTLR]
220 orr r5, r5, #(1 << 3) @ Switch FIQEn on
221 str r5, [r4, #GICC_CTLR]
223 mrc p15, 0, r5, c1, c1, 0 @ Read SCR
224 orr r5, r5, #4 @ Enable FIQ in monitor mode
225 bic r5, r5, #1 @ Secure mode
226 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
229 bl psci_get_cpu_id @ CPU ID => r0
230 bl psci_get_cpu_stack_top @ stack top => r0