git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/sunxi/rsb.c

   1 /*
   2  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   3  *
   4  * Based on allwinner u-boot sources rsb code which is:
   5  * (C) Copyright 2007-2013
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * lixiang <lixiang@allwinnertech.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <errno.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/rsb.h>
  18
  19 static void rsb_cfg_io(void)
  20 {
  21 #ifdef CONFIG_MACH_SUN8I
  22         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
  23         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
  24         sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
  25         sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
  26         sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
  27         sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
  28 #elif defined CONFIG_MACH_SUN9I
  29         sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
  30         sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
  31         sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
  32         sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
  33         sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
  34         sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
  35 #else
  36 #error unsupported MACH_SUNXI
  37 #endif
  38 }
  39
  40 static void rsb_set_clk(void)
  41 {
  42         struct sunxi_rsb_reg * const rsb =
  43                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  44         u32 div = 0;
  45         u32 cd_odly = 0;
  46
  47         /* Source is Hosc24M, set RSB clk to 3Mhz */
  48         div = 24000000 / 3000000 / 2 - 1;
  49         cd_odly = div >> 1;
  50         if (!cd_odly)
  51                 cd_odly = 1;
  52
  53         writel((cd_odly << 8) | div, &rsb->ccr);
  54 }
  55
  56 void rsb_init(void)
  57 {
  58         struct sunxi_rsb_reg * const rsb =
  59                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  60
  61         rsb_cfg_io();
  62
  63         /* Enable RSB and PIO clk, and de-assert their resets */
  64         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
  65
  66         writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
  67         rsb_set_clk();
  68 }
  69
  70 static int rsb_await_trans(void)
  71 {
  72         struct sunxi_rsb_reg * const rsb =
  73                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  74         unsigned long tmo = timer_get_us() + 1000000;
  75         u32 stat;
  76         int ret;
  77
  78         while (1) {
  79                 stat = readl(&rsb->stat);
  80                 if (stat & RSB_STAT_LBSY_INT) {
  81                         ret = -EBUSY;
  82                         break;
  83                 }
  84                 if (stat & RSB_STAT_TERR_INT) {
  85                         ret = -EIO;
  86                         break;
  87                 }
  88                 if (stat & RSB_STAT_TOVER_INT) {
  89                         ret = 0;
  90                         break;
  91                 }
  92                 if (timer_get_us() > tmo) {
  93                         ret = -ETIME;
  94                         break;
  95                 }
  96         }
  97         writel(stat, &rsb->stat); /* Clear status bits */
  98
  99         return ret;
 100 }
 101
 102 int rsb_set_device_mode(u32 device_mode_data)
 103 {
 104         struct sunxi_rsb_reg * const rsb =
 105                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 106         unsigned long tmo = timer_get_us() + 1000000;
 107
 108         writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
 109
 110         while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
 111                 if (timer_get_us() > tmo)
 112                         return -ETIME;
 113         }
 114
 115         return rsb_await_trans();
 116 }
 117
 118 static int rsb_do_trans(void)
 119 {
 120         struct sunxi_rsb_reg * const rsb =
 121                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 122
 123         setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
 124         return rsb_await_trans();
 125 }
 126
 127 int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
 128 {
 129         struct sunxi_rsb_reg * const rsb =
 130                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 131
 132         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
 133                RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
 134         writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
 135
 136         return rsb_do_trans();
 137 }
 138
 139 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
 140 {
 141         struct sunxi_rsb_reg * const rsb =
 142                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 143
 144         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
 145         writel(reg_addr, &rsb->addr);
 146         writel(data, &rsb->data);
 147         writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
 148
 149         return rsb_do_trans();
 150 }
 151
 152 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
 153 {
 154         struct sunxi_rsb_reg * const rsb =
 155                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 156         int ret;
 157
 158         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
 159         writel(reg_addr, &rsb->addr);
 160         writel(RSB_CMD_BYTE_READ, &rsb->cmd);
 161
 162         ret = rsb_do_trans();
 163         if (ret)
 164                 return ret;
 165
 166         *data = readl(&rsb->data) & 0xff;
 167
 168         return 0;
 169 }