4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/usb_phy.h>
21 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800
22 #ifdef CONFIG_MACH_SUN8I_A33
23 #define SUNXI_USB_CSR 0x410
25 #define SUNXI_USB_CSR 0x404
27 #define SUNXI_USB_PASSBY_EN 1
29 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
30 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
31 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
32 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
34 #define REG_PHY_UNK_H3 0x420
35 #define REG_PMU_UNK_H3 0x810
37 static struct sunxi_usb_phy {
48 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
50 .base = SUNXI_USB0_BASE,
53 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
55 .base = SUNXI_USB1_BASE,
57 #if CONFIG_SUNXI_USB_PHYS >= 3
59 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
61 .base = SUNXI_USB2_BASE,
64 #if CONFIG_SUNXI_USB_PHYS >= 4
66 .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
68 .base = SUNXI_USB3_BASE,
73 static int get_vbus_gpio(int index)
76 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
77 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
78 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
79 case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
84 static int get_vbus_detect_gpio(int index)
87 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
92 static int get_id_detect_gpio(int index)
95 case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
100 static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
103 int j = 0, usbc_bit = 0;
104 void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
106 #ifdef CONFIG_MACH_SUN8I_A33
107 /* CSR needs to be explicitly initialized to 0 on A33 */
111 usbc_bit = 1 << (phy->id * 2);
112 for (j = 0; j < len; j++) {
113 /* set the bit address to be written */
114 clrbits_le32(dest, 0xff << 8);
115 setbits_le32(dest, (addr + j) << 8);
117 clrbits_le32(dest, usbc_bit);
120 setbits_le32(dest, 1 << 7);
122 clrbits_le32(dest, 1 << 7);
124 setbits_le32(dest, usbc_bit);
126 clrbits_le32(dest, usbc_bit);
132 #if defined CONFIG_MACH_SUN8I_H3
133 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
136 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
138 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
141 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
143 /* The following comments are machine
144 * translated from Chinese, you have been warned!
147 /* Regulation 45 ohms */
149 usb_phy_write(phy, 0x0c, 0x01, 1);
151 /* adjust PHY's magnitude and rate */
152 usb_phy_write(phy, 0x20, 0x14, 5);
154 /* threshold adjustment disconnect */
155 #if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
156 usb_phy_write(phy, 0x2a, 2, 2);
158 usb_phy_write(phy, 0x2a, 3, 2);
165 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
167 unsigned long bits = 0;
170 addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
172 bits = SUNXI_EHCI_AHB_ICHR8_EN |
173 SUNXI_EHCI_AHB_INCR4_BURST_EN |
174 SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
175 SUNXI_EHCI_ULPI_BYPASS_EN;
178 setbits_le32(addr, bits);
180 clrbits_le32(addr, bits);
185 void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
187 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
189 usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
192 void sunxi_usb_phy_init(int index)
194 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
195 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
198 if (phy->init_count != 1)
201 setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
203 sunxi_usb_phy_config(phy);
206 sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
209 void sunxi_usb_phy_exit(int index)
211 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
212 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
215 if (phy->init_count != 0)
219 sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
221 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
224 void sunxi_usb_phy_power_on(int index)
226 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
228 phy->power_on_count++;
229 if (phy->power_on_count != 1)
232 if (phy->gpio_vbus >= 0)
233 gpio_set_value(phy->gpio_vbus, 1);
236 void sunxi_usb_phy_power_off(int index)
238 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
240 phy->power_on_count--;
241 if (phy->power_on_count != 0)
244 if (phy->gpio_vbus >= 0)
245 gpio_set_value(phy->gpio_vbus, 0);
248 int sunxi_usb_phy_power_is_on(int index)
250 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
252 return phy->power_on_count > 0;
255 int sunxi_usb_phy_vbus_detect(int index)
257 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
258 int err, retries = 3;
260 if (phy->gpio_vbus_det < 0)
261 return phy->gpio_vbus_det;
263 err = gpio_get_value(phy->gpio_vbus_det);
265 * Vbus may have been provided by the board and just been turned of
266 * some milliseconds ago on reset, what we're measuring then is a
267 * residual charge on Vbus, sleep a bit and try again.
269 while (err > 0 && retries--) {
271 err = gpio_get_value(phy->gpio_vbus_det);
277 int sunxi_usb_phy_id_detect(int index)
279 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
281 if (phy->gpio_id_det < 0)
282 return phy->gpio_id_det;
284 return gpio_get_value(phy->gpio_id_det);
287 int sunxi_usb_phy_probe(void)
289 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
290 struct sunxi_usb_phy *phy;
293 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
294 phy = &sunxi_usb_phy[i];
296 phy->gpio_vbus = get_vbus_gpio(i);
297 if (phy->gpio_vbus >= 0) {
298 ret = gpio_request(phy->gpio_vbus, "usb_vbus");
301 ret = gpio_direction_output(phy->gpio_vbus, 0);
306 phy->gpio_vbus_det = get_vbus_detect_gpio(i);
307 if (phy->gpio_vbus_det >= 0) {
308 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
311 ret = gpio_direction_input(phy->gpio_vbus_det);
316 phy->gpio_id_det = get_id_detect_gpio(i);
317 if (phy->gpio_id_det >= 0) {
318 ret = gpio_request(phy->gpio_id_det, "usb_id_det");
321 ret = gpio_direction_input(phy->gpio_id_det);
324 sunxi_gpio_set_pull(phy->gpio_id_det,
329 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
334 int sunxi_usb_phy_remove(void)
336 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
337 struct sunxi_usb_phy *phy;
340 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
342 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
343 phy = &sunxi_usb_phy[i];
345 if (phy->gpio_vbus >= 0)
346 gpio_free(phy->gpio_vbus);
348 if (phy->gpio_vbus_det >= 0)
349 gpio_free(phy->gpio_vbus_det);
351 if (phy->gpio_id_det >= 0)
352 gpio_free(phy->gpio_id_det);