2 * SoC-specific setup info
4 * (C) Copyright 2010,2011
5 * NVIDIA Corporation <www.nvidia.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
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21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
33 .global invalidate_dcache
40 ldr r1, rstctl @ get addr for global reset
44 str r3, [r1] @ force reset
56 bl s_init @ go setup pll, mux & memory
60 mov pc, lr @ back to arch calling code
65 @ Initialize the AVP, clocks, and memory controller
66 @ SDRAM is guaranteed to be on at this point
68 ldr r0, =cold_boot @ R0 = reset vector for CPU
69 bl start_cpu @ start the CPU
71 @ Transfer control to the AVP code
74 @ Should never get here
78 .globl cache_configure
81 @ invalidate instruction cache
83 mcr p15, 0, r1, c7, c5, 0
85 @ invalidate the i&d tlb entries
86 mcr p15, 0, r1, c8, c5, 0
87 mcr p15, 0, r1, c8, c6, 0
89 @ enable instruction cache
90 mrc p15, 0, r1, c1, c0, 0
92 mcr p15, 0, r1, c1, c0, 0
96 @ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg
97 mrc p15, 0, r0, c1, c0, 1
99 mcr p15, 0, r0, c1, c0, 1
101 @ Now flush the Dcache
109 @ invalidate d-cache using line (way0)
110 mcr p15, 0, r0, c7, c6, 2
113 @ invalidate d-cache using line (way1)
114 mcr p15, 0, r2, c7, c6, 2
117 @ invalidate d-cache using line (way2)
118 mcr p15, 0, r2, c7, c6, 2
121 @ invalidate d-cache using line (way3)
122 mcr p15, 0, r2, c7, c6, 2
126 @ FIXME: should have ap20's L2 disabled too?
133 @ Check current processor: CPU or AVP?
134 @ If CPU, go to CPU boot code, else continue on AVP path
136 ldr r0, =NV_PA_PG_UP_BASE
138 ldr r2, =PG_UP_TAG_AVP
143 @ yep, we are the CPU
146 @ AVP initialization follows this path
148 @ Init AVP and start CPU
151 @ the literal pools origin
155 .word LOW_LEVEL_SRAM_STACK
157 .word EARLY_AVP_STACK
159 .word EARLY_CPU_STACK