2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm-generic/gpio.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/pinmux.h>
30 #include <asm/arch/tegra.h>
31 #include <asm/arch/usb.h>
33 #include <asm/arch-tegra/clk_rst.h>
34 #include <asm/arch-tegra/sys_proto.h>
35 #include <asm/arch-tegra/uart.h>
39 #ifdef CONFIG_USB_ULPI
40 #ifndef CONFIG_USB_ULPI_VIEWPORT
41 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
42 define CONFIG_USB_ULPI_VIEWPORT"
47 USB_PORTS_MAX = 4, /* Maximum ports we allow */
50 /* Parameters we need for USB */
52 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
53 PARAM_DIVM, /* PLL INPUT DIVIDER */
54 PARAM_DIVP, /* POST DIVIDER (2^N) */
55 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
56 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
57 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
58 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
59 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
60 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
61 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
62 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
67 /* Possible port types (dual role mode) */
70 DR_MODE_HOST, /* supports host operation */
71 DR_MODE_DEVICE, /* supports device operation */
72 DR_MODE_OTG, /* supports both */
75 /* Information about a USB port */
77 struct usb_ctlr *reg; /* address of registers in physical memory */
78 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
79 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
80 unsigned enabled:1; /* 1 to enable, 0 to disable */
81 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
82 enum dr_mode dr_mode; /* dual role mode */
83 enum periph_id periph_id;/* peripheral id */
84 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
85 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
89 static unsigned port_count; /* Number of available ports */
92 * This table has USB timing parameters for each Oscillator frequency we
93 * support. There are four sets of values:
95 * 1. PLLU configuration information (reference clock is osc/clk_m and
96 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
98 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
99 * ----------------------------------------------------------------------
100 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
101 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
102 * Filter frequency (MHz) 1 4.8 6 2
103 * CPCON 1100b 0011b 1100b 1100b
106 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
108 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
109 * ---------------------------------------------------------------------------
110 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
111 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
112 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
113 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
115 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
116 * SessEnd. Each of these signals have their own debouncer and for each of
117 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
120 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
121 * 0xffff -> No debouncing at all
122 * <n> ms = <n> *1000 / (1/19.2MHz) / 4
124 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
125 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
127 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
128 * values, so we can keep those to default.
130 * 4. The 20 microsecond delay after bias cell operation.
132 static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
133 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
134 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
135 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
136 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
137 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
140 /* UTMIP Idle Wait Delay */
141 static const u8 utmip_idle_wait_delay = 17;
143 /* UTMIP Elastic limit */
144 static const u8 utmip_elastic_limit = 16;
146 /* UTMIP High Speed Sync Start Delay */
147 static const u8 utmip_hs_sync_start_delay = 9;
149 /* Put the port into host mode */
150 static void set_host_mode(struct fdt_usb *config)
153 * If we are an OTG port, check if remote host is driving VBus and
154 * bail out in this case.
156 if (config->dr_mode == DR_MODE_OTG &&
157 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
161 * If not driving, we set the GPIO to enable VBUS. We assume
162 * that the pinmux is set up correctly for this.
164 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
165 fdtdec_setup_gpio(&config->vbus_gpio);
166 gpio_direction_output(config->vbus_gpio.gpio,
167 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
169 debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
170 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
175 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
177 /* Reset the USB controller with 2us delay */
178 reset_periph(config->periph_id, 2);
181 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
184 if (config->has_legacy_mode)
185 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
187 /* Put UTMIP1/3 in reset */
188 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
190 /* Enable the UTMIP PHY */
192 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
195 * TODO: where do we take the USB1 out of reset? The old code would
196 * take USB3 out of reset, but not USB1. This code doesn't do either.
200 /* set up the UTMI USB controller with the parameters provided */
201 static int init_utmi_usb_controller(struct fdt_usb *config,
202 struct usb_ctlr *usbctlr, const u32 timing[])
207 clock_enable(config->periph_id);
209 /* Reset the usb controller */
210 usbf_reset_controller(config, usbctlr);
212 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
213 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
215 /* Follow the crystal clock disable by >100ns delay */
219 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
220 * mux must be switched to actually use a_sess_vld threshold.
222 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
223 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
225 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
229 * PLL Delay CONFIGURATION settings. The following parameters control
230 * the bring up of the plls.
232 val = readl(&usbctlr->utmip_misc_cfg1);
233 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
234 timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
235 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
236 timing[PARAM_ACTIVE_DELAY_COUNT] <<
237 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
238 writel(val, &usbctlr->utmip_misc_cfg1);
240 /* Set PLL enable delay count and crystal frequency count */
241 val = readl(&usbctlr->utmip_pll_cfg1);
242 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
243 timing[PARAM_ENABLE_DELAY_COUNT] <<
244 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
245 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
246 timing[PARAM_XTAL_FREQ_COUNT] <<
247 UTMIP_XTAL_FREQ_COUNT_SHIFT);
248 writel(val, &usbctlr->utmip_pll_cfg1);
250 /* Setting the tracking length time */
251 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
252 UTMIP_BIAS_PDTRK_COUNT_MASK,
253 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
255 /* Program debounce time for VBUS to become valid */
256 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
257 UTMIP_DEBOUNCE_CFG0_MASK,
258 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
260 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
262 /* Disable battery charge enabling bit */
263 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
265 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
266 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
269 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
270 * Setting these fields, together with default values of the
271 * other fields, results in programming the registers below as
273 * UTMIP_HSRX_CFG0 = 0x9168c000
274 * UTMIP_HSRX_CFG1 = 0x13
277 /* Set PLL enable delay count and Crystal frequency count */
278 val = readl(&usbctlr->utmip_hsrx_cfg0);
279 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
280 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
281 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
282 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
283 writel(val, &usbctlr->utmip_hsrx_cfg0);
285 /* Configure the UTMIP_HS_SYNC_START_DLY */
286 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
287 UTMIP_HS_SYNC_START_DLY_MASK,
288 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
290 /* Preceed the crystal clock disable by >100ns delay. */
293 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
294 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
296 /* Finished the per-controller init. */
298 /* De-assert UTMIP_RESET to bring out of reset. */
299 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
301 /* Wait for the phy clock to become valid in 100 ms */
302 for (loop_count = 100000; loop_count != 0; loop_count--) {
303 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
310 /* Disable ICUSB FS/LS transceiver */
311 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
313 /* Select UTMI parallel interface */
314 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
315 PTS_UTMI << PTS_SHIFT);
316 clrbits_le32(&usbctlr->port_sc1, STS);
318 /* Deassert power down state */
319 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
320 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
321 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
322 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
327 #ifdef CONFIG_USB_ULPI
328 /* if board file does not set a ULPI reference frequency we default to 24MHz */
329 #ifndef CONFIG_ULPI_REF_CLK
330 #define CONFIG_ULPI_REF_CLK 24000000
333 /* set up the ULPI USB controller with the parameters provided */
334 static int init_ulpi_usb_controller(struct fdt_usb *config,
335 struct usb_ctlr *usbctlr)
339 struct ulpi_viewport ulpi_vp;
341 /* set up ULPI reference clock on pllp_out4 */
342 clock_enable(PERIPH_ID_DEV2_OUT);
343 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
346 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
347 fdtdec_setup_gpio(&config->phy_reset_gpio);
348 gpio_direction_output(config->phy_reset_gpio.gpio, 0);
350 gpio_set_value(config->phy_reset_gpio.gpio, 1);
353 /* Reset the usb controller */
354 clock_enable(config->periph_id);
355 usbf_reset_controller(config, usbctlr);
357 /* enable pinmux bypass */
358 setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
359 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
361 /* Select ULPI parallel interface */
362 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
364 /* enable ULPI transceiver */
365 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
367 /* configure ULPI transceiver timings */
369 writel(val, &usbctlr->ulpi_timing_ctrl_1);
371 val |= ULPI_DATA_TRIMMER_SEL(4);
372 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
373 val |= ULPI_DIR_TRIMMER_SEL(4);
374 writel(val, &usbctlr->ulpi_timing_ctrl_1);
377 val |= ULPI_DATA_TRIMMER_LOAD;
378 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
379 val |= ULPI_DIR_TRIMMER_LOAD;
380 writel(val, &usbctlr->ulpi_timing_ctrl_1);
382 /* set up phy for host operation with external vbus supply */
383 ulpi_vp.port_num = 0;
384 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
386 if (ulpi_init(&ulpi_vp)) {
387 printf("Tegra ULPI viewport init failed\n");
391 ulpi_set_vbus(&ulpi_vp, 1, 1);
392 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
394 /* enable wakeup events */
395 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
397 /* Enable and wait for the phy clock to become valid in 100 ms */
398 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
399 for (loop_count = 100000; loop_count != 0; loop_count--) {
400 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
406 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
411 static int init_ulpi_usb_controller(struct fdt_usb *config,
412 struct usb_ctlr *usbctlr)
414 printf("No code to set up ULPI controller, please enable"
415 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
420 static void config_clock(const u32 timing[])
422 clock_start_pll(CLOCK_ID_USB,
423 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
424 timing[PARAM_CPCON], timing[PARAM_LFCON]);
428 * Add a new USB port to the list of available ports.
430 * @param config USB port configuration
431 * @return 0 if ok, -1 if error (too many ports)
433 static int add_port(struct fdt_usb *config, const u32 timing[])
435 struct usb_ctlr *usbctlr = config->reg;
437 if (port_count == USB_PORTS_MAX) {
438 printf("tegrausb: Cannot register more than %d ports\n",
443 if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
444 printf("tegrausb: Cannot init port\n");
448 if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
449 printf("tegrausb: Cannot init port\n");
453 port[port_count++] = *config;
458 int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
460 struct usb_ctlr *usbctlr;
462 if (portnum >= port_count)
464 set_host_mode(&port[portnum]);
466 usbctlr = port[portnum].reg;
467 *hccr = (u32)&usbctlr->cap_length;
468 *hcor = (u32)&usbctlr->usb_cmd;
472 int tegrausb_stop_port(int portnum)
474 struct usb_ctlr *usbctlr;
476 usbctlr = port[portnum].reg;
478 /* Stop controller */
479 writel(0, &usbctlr->usb_cmd);
482 /* Initiate controller reset */
483 writel(2, &usbctlr->usb_cmd);
489 int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
490 struct fdt_usb *config)
492 const char *phy, *mode;
494 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
495 mode = fdt_getprop(blob, node, "dr_mode", NULL);
497 if (0 == strcmp(mode, "host"))
498 config->dr_mode = DR_MODE_HOST;
499 else if (0 == strcmp(mode, "peripheral"))
500 config->dr_mode = DR_MODE_DEVICE;
501 else if (0 == strcmp(mode, "otg"))
502 config->dr_mode = DR_MODE_OTG;
504 debug("%s: Cannot decode dr_mode '%s'\n", __func__,
506 return -FDT_ERR_NOTFOUND;
509 config->dr_mode = DR_MODE_HOST;
512 phy = fdt_getprop(blob, node, "phy_type", NULL);
513 config->utmi = phy && 0 == strcmp("utmi", phy);
514 config->ulpi = phy && 0 == strcmp("ulpi", phy);
515 config->enabled = fdtdec_get_is_enabled(blob, node);
516 config->has_legacy_mode = fdtdec_get_bool(blob, node,
517 "nvidia,has-legacy-mode");
518 config->periph_id = clock_decode_periph_id(blob, node);
519 if (config->periph_id == PERIPH_ID_NONE) {
520 debug("%s: Missing/invalid peripheral ID\n", __func__);
521 return -FDT_ERR_NOTFOUND;
523 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
524 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
525 &config->phy_reset_gpio);
526 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
527 "vbus=%d, phy_reset=%d, dr_mode=%d\n",
528 config->enabled, config->has_legacy_mode, config->utmi,
529 config->ulpi, config->periph_id, config->vbus_gpio.gpio,
530 config->phy_reset_gpio.gpio, config->dr_mode);
535 int board_usb_init(const void *blob)
537 struct fdt_usb config;
538 unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
539 enum clock_osc_freq freq;
540 int node_list[USB_PORTS_MAX];
543 /* Set up the USB clocks correctly based on our oscillator frequency */
544 freq = clock_get_osc_freq();
545 config_clock(usb_pll[freq]);
547 /* count may return <0 on error */
548 count = fdtdec_find_aliases_for_id(blob, "usb",
549 COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
550 for (i = 0; i < count; i++) {
551 debug("USB %d: ", i);
555 if (fdt_decode_usb(blob, node, osc_freq, &config)) {
556 debug("Cannot decode USB node %s\n",
557 fdt_get_name(blob, node, NULL));
561 if (add_port(&config, usb_pll[freq]))
563 set_host_mode(&config);