2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm-generic/gpio.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/pinmux.h>
30 #include <asm/arch/tegra.h>
31 #include <asm/arch/usb.h>
33 #include <asm/arch-tegra/clk_rst.h>
34 #include <asm/arch-tegra/sys_proto.h>
35 #include <asm/arch-tegra/uart.h>
39 #ifdef CONFIG_USB_ULPI
40 #ifndef CONFIG_USB_ULPI_VIEWPORT
41 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
42 define CONFIG_USB_ULPI_VIEWPORT"
47 USB_PORTS_MAX = 3, /* Maximum ports we allow */
50 /* Parameters we need for USB */
52 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
53 PARAM_DIVM, /* PLL INPUT DIVIDER */
54 PARAM_DIVP, /* POST DIVIDER (2^N) */
55 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
56 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
57 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
58 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
59 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
60 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
61 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
62 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
67 /* Possible port types (dual role mode) */
70 DR_MODE_HOST, /* supports host operation */
71 DR_MODE_DEVICE, /* supports device operation */
72 DR_MODE_OTG, /* supports both */
75 /* Information about a USB port */
77 struct usb_ctlr *reg; /* address of registers in physical memory */
78 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
79 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
80 unsigned enabled:1; /* 1 to enable, 0 to disable */
81 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
82 unsigned initialized:1; /* has this port already been initialized? */
83 enum dr_mode dr_mode; /* dual role mode */
84 enum periph_id periph_id;/* peripheral id */
85 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
86 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
89 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
90 static unsigned port_count; /* Number of available ports */
93 * This table has USB timing parameters for each Oscillator frequency we
94 * support. There are four sets of values:
96 * 1. PLLU configuration information (reference clock is osc/clk_m and
97 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
99 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
100 * ----------------------------------------------------------------------
101 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
102 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
103 * Filter frequency (MHz) 1 4.8 6 2
104 * CPCON 1100b 0011b 1100b 1100b
107 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
109 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
110 * ---------------------------------------------------------------------------
111 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
112 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
113 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
114 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
116 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
117 * SessEnd. Each of these signals have their own debouncer and for each of
118 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
121 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
122 * 0xffff -> No debouncing at all
123 * <n> ms = <n> *1000 / (1/19.2MHz) / 4
125 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
126 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
128 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
129 * values, so we can keep those to default.
131 * 4. The 20 microsecond delay after bias cell operation.
133 static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
134 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
135 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
136 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
137 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
138 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
141 /* UTMIP Idle Wait Delay */
142 static const u8 utmip_idle_wait_delay = 17;
144 /* UTMIP Elastic limit */
145 static const u8 utmip_elastic_limit = 16;
147 /* UTMIP High Speed Sync Start Delay */
148 static const u8 utmip_hs_sync_start_delay = 9;
150 /* Put the port into host mode */
151 static void set_host_mode(struct fdt_usb *config)
154 * If we are an OTG port, check if remote host is driving VBus and
155 * bail out in this case.
157 if (config->dr_mode == DR_MODE_OTG &&
158 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
162 * If not driving, we set the GPIO to enable VBUS. We assume
163 * that the pinmux is set up correctly for this.
165 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
166 fdtdec_setup_gpio(&config->vbus_gpio);
167 gpio_direction_output(config->vbus_gpio.gpio,
168 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
170 debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
171 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
176 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
178 /* Reset the USB controller with 2us delay */
179 reset_periph(config->periph_id, 2);
182 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
185 if (config->has_legacy_mode)
186 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
188 /* Put UTMIP1/3 in reset */
189 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
191 /* Enable the UTMIP PHY */
193 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
196 * TODO: where do we take the USB1 out of reset? The old code would
197 * take USB3 out of reset, but not USB1. This code doesn't do either.
201 /* set up the UTMI USB controller with the parameters provided */
202 static int init_utmi_usb_controller(struct fdt_usb *config)
206 const unsigned *timing;
207 struct usb_ctlr *usbctlr = config->reg;
209 clock_enable(config->periph_id);
211 /* Reset the usb controller */
212 usbf_reset_controller(config, usbctlr);
214 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
215 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
217 /* Follow the crystal clock disable by >100ns delay */
221 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
222 * mux must be switched to actually use a_sess_vld threshold.
224 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
225 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
227 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
231 * PLL Delay CONFIGURATION settings. The following parameters control
232 * the bring up of the plls.
234 timing = usb_pll[clock_get_osc_freq()];
236 val = readl(&usbctlr->utmip_misc_cfg1);
237 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
238 timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
239 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
240 timing[PARAM_ACTIVE_DELAY_COUNT] <<
241 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
242 writel(val, &usbctlr->utmip_misc_cfg1);
244 /* Set PLL enable delay count and crystal frequency count */
245 val = readl(&usbctlr->utmip_pll_cfg1);
246 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
247 timing[PARAM_ENABLE_DELAY_COUNT] <<
248 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
249 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
250 timing[PARAM_XTAL_FREQ_COUNT] <<
251 UTMIP_XTAL_FREQ_COUNT_SHIFT);
252 writel(val, &usbctlr->utmip_pll_cfg1);
254 /* Setting the tracking length time */
255 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
256 UTMIP_BIAS_PDTRK_COUNT_MASK,
257 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
259 /* Program debounce time for VBUS to become valid */
260 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
261 UTMIP_DEBOUNCE_CFG0_MASK,
262 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
264 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
266 /* Disable battery charge enabling bit */
267 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
269 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
270 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
273 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
274 * Setting these fields, together with default values of the
275 * other fields, results in programming the registers below as
277 * UTMIP_HSRX_CFG0 = 0x9168c000
278 * UTMIP_HSRX_CFG1 = 0x13
281 /* Set PLL enable delay count and Crystal frequency count */
282 val = readl(&usbctlr->utmip_hsrx_cfg0);
283 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
284 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
285 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
286 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
287 writel(val, &usbctlr->utmip_hsrx_cfg0);
289 /* Configure the UTMIP_HS_SYNC_START_DLY */
290 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
291 UTMIP_HS_SYNC_START_DLY_MASK,
292 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
294 /* Preceed the crystal clock disable by >100ns delay. */
297 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
298 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
300 /* Finished the per-controller init. */
302 /* De-assert UTMIP_RESET to bring out of reset. */
303 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
305 /* Wait for the phy clock to become valid in 100 ms */
306 for (loop_count = 100000; loop_count != 0; loop_count--) {
307 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
314 /* Disable ICUSB FS/LS transceiver */
315 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
317 /* Select UTMI parallel interface */
318 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
319 PTS_UTMI << PTS_SHIFT);
320 clrbits_le32(&usbctlr->port_sc1, STS);
322 /* Deassert power down state */
323 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
324 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
325 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
326 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
331 #ifdef CONFIG_USB_ULPI
332 /* if board file does not set a ULPI reference frequency we default to 24MHz */
333 #ifndef CONFIG_ULPI_REF_CLK
334 #define CONFIG_ULPI_REF_CLK 24000000
337 /* set up the ULPI USB controller with the parameters provided */
338 static int init_ulpi_usb_controller(struct fdt_usb *config)
342 struct ulpi_viewport ulpi_vp;
343 struct usb_ctlr *usbctlr = config->reg;
345 /* set up ULPI reference clock on pllp_out4 */
346 clock_enable(PERIPH_ID_DEV2_OUT);
347 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
350 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
351 fdtdec_setup_gpio(&config->phy_reset_gpio);
352 gpio_direction_output(config->phy_reset_gpio.gpio, 0);
354 gpio_set_value(config->phy_reset_gpio.gpio, 1);
357 /* Reset the usb controller */
358 clock_enable(config->periph_id);
359 usbf_reset_controller(config, usbctlr);
361 /* enable pinmux bypass */
362 setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
363 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
365 /* Select ULPI parallel interface */
366 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
368 /* enable ULPI transceiver */
369 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
371 /* configure ULPI transceiver timings */
373 writel(val, &usbctlr->ulpi_timing_ctrl_1);
375 val |= ULPI_DATA_TRIMMER_SEL(4);
376 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
377 val |= ULPI_DIR_TRIMMER_SEL(4);
378 writel(val, &usbctlr->ulpi_timing_ctrl_1);
381 val |= ULPI_DATA_TRIMMER_LOAD;
382 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
383 val |= ULPI_DIR_TRIMMER_LOAD;
384 writel(val, &usbctlr->ulpi_timing_ctrl_1);
386 /* set up phy for host operation with external vbus supply */
387 ulpi_vp.port_num = 0;
388 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
390 if (ulpi_init(&ulpi_vp)) {
391 printf("Tegra ULPI viewport init failed\n");
395 ulpi_set_vbus(&ulpi_vp, 1, 1);
396 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
398 /* enable wakeup events */
399 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
401 /* Enable and wait for the phy clock to become valid in 100 ms */
402 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
403 for (loop_count = 100000; loop_count != 0; loop_count--) {
404 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
410 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
415 static int init_ulpi_usb_controller(struct fdt_usb *config)
417 printf("No code to set up ULPI controller, please enable"
418 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
423 static void config_clock(const u32 timing[])
425 clock_start_pll(CLOCK_ID_USB,
426 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
427 timing[PARAM_CPCON], timing[PARAM_LFCON]);
430 int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
432 struct fdt_usb *config;
433 struct usb_ctlr *usbctlr;
435 if (portnum >= port_count)
438 config = &port[portnum];
440 /* skip init, if the port is already initialized */
441 if (config->initialized)
444 if (config->utmi && init_utmi_usb_controller(config)) {
445 printf("tegrausb: Cannot init port %d\n", portnum);
449 if (config->ulpi && init_ulpi_usb_controller(config)) {
450 printf("tegrausb: Cannot init port %d\n", portnum);
454 set_host_mode(config);
456 config->initialized = 1;
459 usbctlr = config->reg;
460 *hccr = (u32)&usbctlr->cap_length;
461 *hcor = (u32)&usbctlr->usb_cmd;
465 int tegrausb_stop_port(int portnum)
467 struct usb_ctlr *usbctlr;
469 usbctlr = port[portnum].reg;
471 /* Stop controller */
472 writel(0, &usbctlr->usb_cmd);
475 /* Initiate controller reset */
476 writel(2, &usbctlr->usb_cmd);
479 port[portnum].initialized = 0;
484 int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
486 const char *phy, *mode;
488 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
489 mode = fdt_getprop(blob, node, "dr_mode", NULL);
491 if (0 == strcmp(mode, "host"))
492 config->dr_mode = DR_MODE_HOST;
493 else if (0 == strcmp(mode, "peripheral"))
494 config->dr_mode = DR_MODE_DEVICE;
495 else if (0 == strcmp(mode, "otg"))
496 config->dr_mode = DR_MODE_OTG;
498 debug("%s: Cannot decode dr_mode '%s'\n", __func__,
500 return -FDT_ERR_NOTFOUND;
503 config->dr_mode = DR_MODE_HOST;
506 phy = fdt_getprop(blob, node, "phy_type", NULL);
507 config->utmi = phy && 0 == strcmp("utmi", phy);
508 config->ulpi = phy && 0 == strcmp("ulpi", phy);
509 config->enabled = fdtdec_get_is_enabled(blob, node);
510 config->has_legacy_mode = fdtdec_get_bool(blob, node,
511 "nvidia,has-legacy-mode");
512 config->periph_id = clock_decode_periph_id(blob, node);
513 if (config->periph_id == PERIPH_ID_NONE) {
514 debug("%s: Missing/invalid peripheral ID\n", __func__);
515 return -FDT_ERR_NOTFOUND;
517 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
518 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
519 &config->phy_reset_gpio);
520 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
521 "vbus=%d, phy_reset=%d, dr_mode=%d\n",
522 config->enabled, config->has_legacy_mode, config->utmi,
523 config->ulpi, config->periph_id, config->vbus_gpio.gpio,
524 config->phy_reset_gpio.gpio, config->dr_mode);
529 int board_usb_init(const void *blob)
531 struct fdt_usb config;
532 enum clock_osc_freq freq;
533 int node_list[USB_PORTS_MAX];
536 /* Set up the USB clocks correctly based on our oscillator frequency */
537 freq = clock_get_osc_freq();
538 config_clock(usb_pll[freq]);
540 /* count may return <0 on error */
541 count = fdtdec_find_aliases_for_id(blob, "usb",
542 COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
543 for (i = 0; i < count; i++) {
544 if (port_count == USB_PORTS_MAX) {
545 printf("tegrausb: Cannot register more than %d ports\n",
550 debug("USB %d: ", i);
554 if (fdt_decode_usb(blob, node, &config)) {
555 debug("Cannot decode USB node %s\n",
556 fdt_get_name(blob, node, NULL));
559 config.initialized = 0;
561 /* add new USB port to the list of available ports */
562 port[port_count++] = config;