2 * Copyright (C) 2012 Linaro Limited
3 * Mathieu Poirier <mathieu.poirier@linaro.org>
5 * Based on original code from Joakim Axelsson at ST-Ericsson
6 * (C) Copyright 2010 ST-Ericsson
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/prcmu.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/hardware.h>
33 #include <asm/arch/hardware.h>
35 #define CPUID_DB8500V1 0x411fc091
36 #define CPUID_DB8500V2 0x412fc091
37 #define ASICID_DB8500V11 0x008500A1
39 #define CACHE_CONTR_BASE 0xA0412000
40 /* Cache controller register offsets
41 * as found in ARM's technical reference manual
43 #define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
44 #define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
45 #define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
47 static unsigned int read_asicid(void);
49 static inline unsigned int read_cpuid(void)
53 /* Main ID register (MIDR) */
54 asm("mrc p15, 0, %0, c0, c0, 0"
62 static int cpu_is_u8500v11(void)
64 return read_asicid() == ASICID_DB8500V11;
67 static int cpu_is_u8500v2(void)
69 return read_cpuid() == CPUID_DB8500V2;
72 static unsigned int read_asicid(void)
74 unsigned int *address;
77 address = (void *) U8500_ASIC_ID_LOC_V2;
79 address = (void *) U8500_ASIC_ID_LOC_ED_V1;
81 return readl(address);
84 void cpu_cache_initialization(void)
87 /* invalidate all cache entries */
88 writel(0xFFFF, CACHE_INVAL_BY_WAY);
90 /* ways are set to '0' when they are totally
91 * cleaned and invalidated
94 value = readl(CACHE_INVAL_BY_WAY);
95 } while (value & 0xFF);
97 /* Invalidate register 9 D and I lockdown */
98 writel(0xFF, CACHE_LOCKDOWN_BY_D);
99 writel(0xFF, CACHE_LOCKDOWN_BY_I);
102 #ifdef CONFIG_ARCH_CPU_INIT
104 * SOC specific cpu init
106 int arch_cpu_init(void)
109 db8500_clocks_init();
113 #endif /* CONFIG_ARCH_CPU_INIT */
117 int u8500_mmc_power_init(void)
123 if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
126 /* Get AB8500 revision */
127 ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
131 ab8500_revision = ret;
134 * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
135 * card to work. This is done by enabling the regulators in the AB8500
136 * via PRCMU I2C transactions.
138 * This code is derived from the handling of AB8500_LDO_VAUX3 in
139 * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
141 * Turn off and delay is required to have it work across soft reboots.
144 /* Turn off (read-modify-write) */
145 ret = ab8500_read(AB8500_REGU_CTRL2,
146 AB8500_REGU_VRF1VAUX3_REGU_REG);
153 ret = ab8500_write(AB8500_REGU_CTRL2,
154 AB8500_REGU_VRF1VAUX3_REGU_REG,
155 enable & ~LDO_VAUX3_ENABLE_MASK);
161 /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
162 ret = ab8500_read(AB8500_REGU_CTRL2,
163 AB8500_REGU_VRF1VAUX3_SEL_REG);
169 if (ab8500_revision < 0x20) {
170 voltage &= ~LDO_VAUX3_SEL_MASK;
171 voltage |= LDO_VAUX3_SEL_2V9;
173 voltage &= ~LDO_VAUX3_V2_SEL_MASK;
174 voltage |= LDO_VAUX3_V2_SEL_2V91;
177 ret = ab8500_write(AB8500_REGU_CTRL2,
178 AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
182 /* Turn on the supply */
183 enable &= ~LDO_VAUX3_ENABLE_MASK;
184 enable |= LDO_VAUX3_ENABLE_VAL;
186 ret = ab8500_write(AB8500_REGU_CTRL2,
187 AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
192 #endif /* CONFIG_MMC */