2 * Copyright (C) 2009 ST-Ericsson SA
4 * Adapted from the Linux version:
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 * NOTE: This currently does not support the I2C workaround access method.
17 #include <asm/arch/hardware.h>
18 #include <asm/types.h>
20 #include <asm/errno.h>
21 #include <asm/arch/prcmu.h>
23 /* CPU mailbox registers */
24 #define PRCMU_I2C_WRITE(slave) \
25 (((slave) << 1) | I2CWRITE | (1 << 6))
26 #define PRCMU_I2C_READ(slave) \
27 (((slave) << 1) | I2CREAD | (1 << 6))
29 #define I2C_MBOX_BIT (1 << 5)
31 static int prcmu_is_ready(void)
33 int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
35 printf("PRCMU firmware not ready\n");
39 static int wait_for_i2c_mbx_rdy(void)
43 if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
44 printf("prcmu: warning i2c mailbox was not acked\n");
45 /* clear mailbox 5 ack irq */
46 writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
49 /* check any already on-going transaction */
50 while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
59 static int wait_for_i2c_req_done(void)
63 /* Set an interrupt to XP70 */
64 writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
66 /* wait for mailbox 5 (i2c) ack */
67 while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
77 * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
78 * @reg: - db8500 register bank to be accessed
79 * @slave: - db8500 register to be accessed
80 * Returns: ACK_MB5 value containing the status
82 int prcmu_i2c_read(u8 reg, u16 slave)
88 if (!prcmu_is_ready())
91 debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
94 ret = wait_for_i2c_mbx_rdy();
96 printf("prcmu_i2c_read: mailbox became not ready\n");
100 /* prepare the data for mailbox 5 */
101 writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
102 writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
103 writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
104 writeb(0, PRCM_REQ_MB5_I2CVAL);
106 ret = wait_for_i2c_req_done();
108 printf("prcmu_i2c_read: mailbox request timed out\n");
112 /* retrieve values */
113 debug("ack-mb5:transfer status = %x\n",
114 readb(PRCM_ACK_MB5_STATUS));
115 debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
116 debug("ack-mb5:slave_add = %x\n",
117 readb(PRCM_ACK_MB5_SLAVE));
118 debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
120 i2c_status = readb(PRCM_ACK_MB5_STATUS);
121 i2c_val = readb(PRCM_ACK_MB5_VAL);
122 /* clear mailbox 5 ack irq */
123 writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
125 if (i2c_status == I2C_RD_OK)
128 printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
133 * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
134 * @reg: - db8500 register bank to be accessed
135 * @slave: - db800 register to be written to
136 * @reg_data: - the data to write
137 * Returns: ACK_MB5 value containing the status
139 int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
144 if (!prcmu_is_ready())
147 debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
150 ret = wait_for_i2c_mbx_rdy();
152 printf("prcmu_i2c_write: mailbox became not ready\n");
156 /* prepare the data for mailbox 5 */
157 writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
158 writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
159 writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
160 writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
162 ret = wait_for_i2c_req_done();
164 printf("prcmu_i2c_write: mailbox request timed out\n");
168 /* retrieve values */
169 debug("ack-mb5:transfer status = %x\n",
170 readb(PRCM_ACK_MB5_STATUS));
171 debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
172 debug("ack-mb5:slave_add = %x\n",
173 readb(PRCM_ACK_MB5_SLAVE));
174 debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
176 i2c_status = readb(PRCM_ACK_MB5_STATUS);
177 debug("\ni2c_status = %x\n", i2c_status);
178 /* clear mailbox 5 ack irq */
179 writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
181 if (i2c_status == I2C_WR_OK)
184 printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
188 void u8500_prcmu_enable(u32 *reg)
190 writel(readl(reg) | (1 << 8), reg);
193 void db8500_prcmu_init(void)
196 writel(1 << 17, PRCM_TCR);
198 u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
199 u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
200 u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
201 /* PER4CLK does not exist */
202 u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
203 u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
204 /* Only exists in ED but is always ok to write to */
205 u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
207 u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
208 u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
210 u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
212 /* Clean up the mailbox interrupts after pre-u-boot code. */
213 writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);