2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/bcu-regs.h>
12 #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
18 writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
19 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
20 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
21 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
22 writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
24 /* Specify DDR channel */
25 shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
26 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
29 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
32 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */