2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
13 #ifdef CONFIG_FSL_ESDHC
14 #include <fsl_esdhc.h>
17 #ifdef CONFIG_FSL_ESDHC
18 DECLARE_GLOBAL_DATA_PTR;
21 #ifdef CONFIG_MXC_OCOTP
22 void enable_ocotp_clk(unsigned char enable)
24 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
27 reg = readl(&ccm->ccgr6);
29 reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
31 reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
32 writel(reg, &ccm->ccgr6);
36 static u32 get_mcu_main_clk(void)
38 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
39 u32 ccm_ccsr, ccm_cacrr, armclk_div;
40 u32 sysclk_sel, pll_pfd_sel = 0;
43 ccm_ccsr = readl(&ccm->ccsr);
44 sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
45 sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
47 ccm_cacrr = readl(&ccm->cacrr);
48 armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
49 armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
60 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
61 pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
63 freq = PLL2_MAIN_FREQ;
64 else if (pll_pfd_sel == 1)
65 freq = PLL2_PFD1_FREQ;
66 else if (pll_pfd_sel == 2)
67 freq = PLL2_PFD2_FREQ;
68 else if (pll_pfd_sel == 3)
69 freq = PLL2_PFD3_FREQ;
70 else if (pll_pfd_sel == 4)
71 freq = PLL2_PFD4_FREQ;
74 freq = PLL2_MAIN_FREQ;
77 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
78 pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
80 freq = PLL1_MAIN_FREQ;
81 else if (pll_pfd_sel == 1)
82 freq = PLL1_PFD1_FREQ;
83 else if (pll_pfd_sel == 2)
84 freq = PLL1_PFD2_FREQ;
85 else if (pll_pfd_sel == 3)
86 freq = PLL1_PFD3_FREQ;
87 else if (pll_pfd_sel == 4)
88 freq = PLL1_PFD4_FREQ;
91 freq = PLL3_MAIN_FREQ;
94 printf("unsupported system clock select\n");
97 return freq / armclk_div;
100 static u32 get_bus_clk(void)
102 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
103 u32 ccm_cacrr, busclk_div;
105 ccm_cacrr = readl(&ccm->cacrr);
107 busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
108 busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
111 return get_mcu_main_clk() / busclk_div;
114 static u32 get_ipg_clk(void)
116 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
117 u32 ccm_cacrr, ipgclk_div;
119 ccm_cacrr = readl(&ccm->cacrr);
121 ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
122 ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
125 return get_bus_clk() / ipgclk_div;
128 static u32 get_uart_clk(void)
130 return get_ipg_clk();
133 static u32 get_sdhc_clk(void)
135 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
136 u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
139 ccm_cscmr1 = readl(&ccm->cscmr1);
140 sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
141 sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
143 ccm_cscdr2 = readl(&ccm->cscdr2);
144 sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
145 sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
148 switch (sdhc_clk_sel) {
150 freq = PLL3_MAIN_FREQ;
153 freq = PLL3_PFD3_FREQ;
156 freq = PLL1_PFD3_FREQ;
159 freq = get_bus_clk();
163 return freq / sdhc_clk_div;
166 u32 get_fec_clk(void)
168 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
169 u32 ccm_cscmr2, rmii_clk_sel;
172 ccm_cscmr2 = readl(&ccm->cscmr2);
173 rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
174 rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
176 switch (rmii_clk_sel) {
178 freq = ENET_EXTERNAL_CLK;
181 freq = AUDIO_EXTERNAL_CLK;
184 freq = PLL5_MAIN_FREQ;
187 freq = PLL5_MAIN_FREQ / 2;
194 static u32 get_i2c_clk(void)
196 return get_ipg_clk();
199 unsigned int mxc_get_clock(enum mxc_clock clk)
203 return get_mcu_main_clk();
205 return get_bus_clk();
207 return get_ipg_clk();
209 return get_uart_clk();
211 return get_sdhc_clk();
213 return get_fec_clk();
215 return get_i2c_clk();
222 /* Dump some core clocks */
223 int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
227 printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
228 printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
229 printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
235 clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
240 #ifdef CONFIG_FEC_MXC
241 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
243 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
244 struct fuse_bank *bank = &ocotp->bank[4];
245 struct fuse_bank4_regs *fuse =
246 (struct fuse_bank4_regs *)bank->fuse_regs;
248 u32 value = readl(&fuse->mac_addr0);
249 mac[0] = (value >> 8);
252 value = readl(&fuse->mac_addr1);
253 mac[2] = value >> 24;
254 mac[3] = value >> 16;
260 #if defined(CONFIG_DISPLAY_CPUINFO)
261 static char *get_reset_cause(void)
264 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
266 cause = readl(&src_regs->srsr);
267 writel(cause, &src_regs->srsr);
269 if (cause & SRC_SRSR_POR_RST)
270 return "POWER ON RESET";
271 else if (cause & SRC_SRSR_WDOG_A5)
273 else if (cause & SRC_SRSR_WDOG_M4)
275 else if (cause & SRC_SRSR_JTAG_RST)
276 return "JTAG HIGH-Z";
277 else if (cause & SRC_SRSR_SW_RST)
279 else if (cause & SRC_SRSR_RESETB)
280 return "EXTERNAL RESET";
282 return "unknown reset";
285 int print_cpuinfo(void)
287 printf("CPU: Freescale Vybrid VF610 at %d MHz\n",
288 mxc_get_clock(MXC_ARM_CLK) / 1000000);
289 printf("Reset cause: %s\n", get_reset_cause());
295 int cpu_eth_init(bd_t *bis)
299 #if defined(CONFIG_FEC_MXC)
300 rc = fecmxc_initialize(bis);
306 #ifdef CONFIG_FSL_ESDHC
307 int cpu_mmc_init(bd_t *bis)
309 return fsl_esdhc_mmc_init(bis);
315 #ifdef CONFIG_FSL_ESDHC
316 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);