2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clk.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/hardware.h>
13 void lowlevel_init(void)
17 int arch_cpu_init(void)
20 #ifndef CONFIG_SPL_BUILD
21 /* Device config APB, unlock the PCAP */
22 writel(0x757BDF0D, &devcfg_base->unlock);
23 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
25 #if (CONFIG_SYS_SDRAM_BASE == 0)
26 /* remap DDR to zero, FILTERSTART */
27 writel(0, &scu_base->filter_start);
29 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
30 writel(0x1F, &slcr_base->ocm_cfg);
31 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
32 writel(0x0, &slcr_base->fpga_rst_ctrl);
33 /* Set urgent bits with register */
34 writel(0x0, &slcr_base->ddr_urgent_sel);
35 /* Urgent write, ports S2/S3 */
36 writel(0xC, &slcr_base->ddr_urgent);
39 zynq_clk_early_init();
45 void reset_cpu(ulong addr)
47 zynq_slcr_cpu_reset();
52 #ifndef CONFIG_SYS_DCACHE_OFF
53 void enable_caches(void)
55 /* Enable D-cache. I-cache is already enabled in start.S */