2 * Copyright (c) 2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
12 #define SLCR_LOCK_MAGIC 0x767B
13 #define SLCR_UNLOCK_MAGIC 0xDF0D
15 #define SLCR_IDCODE_MASK 0x1F000
16 #define SLCR_IDCODE_SHIFT 12
18 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
20 void zynq_slcr_lock(void)
23 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
26 void zynq_slcr_unlock(void)
29 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
32 /* Reset the entire system */
33 void zynq_slcr_cpu_reset(void)
36 * Unlock the SLCR then reset the system.
37 * Note that this seems to require raw i/o
38 * functions or there's a lockup?
43 * Clear 0x0F000000 bits of reboot status register to workaround
44 * the FSBL not loading the bitstream after soft-reboot
45 * This is a temporary solution until we know more.
47 clrbits_le32(&slcr_base->reboot_status, 0xF000000);
49 writel(1, &slcr_base->pss_rst_ctrl);
52 /* Setup clk for network */
53 void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
58 printf("Non existing GEM id %d\n", gem_id);
63 /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
64 writel(clk, &slcr_base->gem1_clk_ctrl);
65 /* Configure GEM_RCLK_CTRL */
66 writel(rclk, &slcr_base->gem1_rclk_ctrl);
68 /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
69 writel(clk, &slcr_base->gem0_clk_ctrl);
70 /* Configure GEM_RCLK_CTRL */
71 writel(rclk, &slcr_base->gem0_rclk_ctrl);
78 void zynq_slcr_devcfg_disable(void)
82 /* Disable AXI interface */
83 writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
85 /* Set Level Shifters DT618760 */
86 writel(0xA, &slcr_base->lvl_shftr_en);
91 void zynq_slcr_devcfg_enable(void)
95 /* Set Level Shifters DT618760 */
96 writel(0xF, &slcr_base->lvl_shftr_en);
98 /* Disable AXI interface */
99 writel(0x0, &slcr_base->fpga_rst_ctrl);
104 u32 zynq_slcr_get_idcode(void)
106 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>