2 * Copyright (c) 2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/clk.h>
13 #define SLCR_LOCK_MAGIC 0x767B
14 #define SLCR_UNLOCK_MAGIC 0xDF0D
16 #define SLCR_IDCODE_MASK 0x1F000
17 #define SLCR_IDCODE_SHIFT 12
19 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
21 void zynq_slcr_lock(void)
24 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
27 void zynq_slcr_unlock(void)
30 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
33 /* Reset the entire system */
34 void zynq_slcr_cpu_reset(void)
37 * Unlock the SLCR then reset the system.
38 * Note that this seems to require raw i/o
39 * functions or there's a lockup?
44 * Clear 0x0F000000 bits of reboot status register to workaround
45 * the FSBL not loading the bitstream after soft-reboot
46 * This is a temporary solution until we know more.
48 clrbits_le32(&slcr_base->reboot_status, 0xF000000);
50 writel(1, &slcr_base->pss_rst_ctrl);
53 /* Setup clk for network */
54 void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
61 printf("Non existing GEM id %d\n", gem_id);
65 ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
70 /* Configure GEM_RCLK_CTRL */
71 writel(1, &slcr_base->gem1_rclk_ctrl);
73 /* Configure GEM_RCLK_CTRL */
74 writel(1, &slcr_base->gem0_rclk_ctrl);
81 void zynq_slcr_devcfg_disable(void)
85 /* Disable AXI interface */
86 writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
88 /* Set Level Shifters DT618760 */
89 writel(0xA, &slcr_base->lvl_shftr_en);
94 void zynq_slcr_devcfg_enable(void)
98 /* Set Level Shifters DT618760 */
99 writel(0xF, &slcr_base->lvl_shftr_en);
101 /* Disable AXI interface */
102 writel(0x0, &slcr_base->fpga_rst_ctrl);
107 u32 zynq_slcr_get_boot_mode(void)
109 /* Get the bootmode register value */
110 return readl(&slcr_base->boot_mode);
113 u32 zynq_slcr_get_idcode(void)
115 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>