2 * Copyright (c) 2013 Xilinx Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/hardware.h>
28 #define SLCR_LOCK_MAGIC 0x767B
29 #define SLCR_UNLOCK_MAGIC 0xDF0D
31 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
33 void zynq_slcr_lock(void)
36 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
39 void zynq_slcr_unlock(void)
42 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
45 /* Reset the entire system */
46 void zynq_slcr_cpu_reset(void)
49 * Unlock the SLCR then reset the system.
50 * Note that this seems to require raw i/o
51 * functions or there's a lockup?
56 * Clear 0x0F000000 bits of reboot status register to workaround
57 * the FSBL not loading the bitstream after soft-reboot
58 * This is a temporary solution until we know more.
60 clrbits_le32(&slcr_base->reboot_status, 0xF000000);
62 writel(1, &slcr_base->pss_rst_ctrl);
65 /* Setup clk for network */
66 void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
71 printf("Non existing GEM id %d\n", gem_id);
76 /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
77 writel(clk, &slcr_base->gem1_clk_ctrl);
78 /* Configure GEM_RCLK_CTRL */
79 writel(rclk, &slcr_base->gem1_rclk_ctrl);
81 /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
82 writel(clk, &slcr_base->gem0_clk_ctrl);
83 /* Configure GEM_RCLK_CTRL */
84 writel(rclk, &slcr_base->gem0_rclk_ctrl);