3 * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/bitops.h>
9 #include <asm/armv7m.h>
10 #include <asm/armv7m_mpu.h>
13 #define V7M_MPU_CTRL_ENABLE (1 << 0)
14 #define V7M_MPU_CTRL_DISABLE (0 << 0)
15 #define V7M_MPU_CTRL_HFNMIENA (1 << 1)
16 #define VALID_REGION (1 << 4)
18 #define ENABLE_REGION (1 << 0)
26 #define REGION_SIZE_SHIFT 1
28 #define CACHEABLE (1 << C_SHIFT)
29 #define BUFFERABLE (1 << B_SHIFT)
30 #define SHAREABLE (1 << S_SHIFT)
32 void disable_mpu(void)
34 writel(0, &V7M_MPU->ctrl);
39 writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
41 /* Make sure new mpu config is effective for next memory access */
43 isb(); /* Make sure instruction stream sees it */
46 void mpu_config(struct mpu_region_config *reg_config)
50 switch (reg_config->mr_attr) {
54 case SHARED_WRITE_BUFFERED:
57 case O_I_WT_NO_WR_ALLOC:
60 case O_I_WB_NO_WR_ALLOC:
61 attr = CACHEABLE | BUFFERABLE;
63 case O_I_NON_CACHEABLE:
64 attr = 1 << TEX_SHIFT;
66 case O_I_WB_RD_WR_ALLOC:
67 attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
69 case DEVICE_NON_SHARED:
70 attr = (2 << TEX_SHIFT) | BUFFERABLE;
72 attr = 0; /* strongly ordered */
76 writel(reg_config->start_addr | VALID_REGION | reg_config->region_no,
79 writel(reg_config->xn << XN_SHIFT | reg_config->ap << AP_SHIFT | attr
80 | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION