3 * David Feng <fenghua@phytium.com.cn>
5 * This file is based on sample code from ARMv8 ARM.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm-offsets.h>
12 #include <asm/macro.h>
13 #include <linux/linkage.h>
16 * void __asm_flush_dcache_level(level)
18 * clean and invalidate one level cache.
21 * x1: 0 flush & invalidate, 1 invalidate only
24 ENTRY(__asm_flush_dcache_level)
26 msr csselr_el1, x12 /* select cache level */
27 isb /* sync change of cssidr_el1 */
28 mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
29 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
30 add x2, x2, #4 /* x2 <- log2(cache line size) */
32 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
33 clz w5, w3 /* bit position of #ways */
35 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
36 /* x12 <- cache level << 1 */
37 /* x2 <- line length offset */
38 /* x3 <- number of cache ways - 1 */
39 /* x4 <- number of cache sets - 1 */
40 /* x5 <- bit position of #ways */
43 mov x6, x3 /* x6 <- working copy of #ways */
46 orr x9, x12, x7 /* map way and level to cisw value */
48 orr x9, x9, x7 /* map set number to cisw value */
52 1: dc cisw, x9 /* clean & invalidate by set/way */
53 2: subs x6, x6, #1 /* decrement the way */
55 subs x4, x4, #1 /* decrement the set */
59 ENDPROC(__asm_flush_dcache_level)
62 * void __asm_flush_dcache_all(int invalidate_only)
64 * x0: 0 flush & invalidate, 1 invalidate only
66 * clean and invalidate all data cache by SET/WAY.
68 ENTRY(__asm_dcache_all)
71 mrs x10, clidr_el1 /* read clidr_el1 */
73 and x11, x11, #0x7 /* x11 <- loc */
74 cbz x11, finished /* if loc is 0, exit */
76 mov x0, #0 /* start flush at cache level 0 */
77 /* x0 <- cache level */
78 /* x10 <- clidr_el1 */
80 /* x15 <- return address */
84 add x12, x12, x0 /* x0 <- tripled cache level */
86 and x12, x12, #7 /* x12 <- cache type */
88 b.lt skip /* skip if no cache or icache */
89 bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */
91 add x0, x0, #1 /* increment cache level */
96 msr csselr_el1, x0 /* restore csselr_el1 */
103 ENDPROC(__asm_dcache_all)
105 ENTRY(__asm_flush_dcache_all)
111 ENDPROC(__asm_flush_dcache_all)
113 ENTRY(__asm_invalidate_dcache_all)
119 ENDPROC(__asm_invalidate_dcache_all)
122 * void __asm_flush_dcache_range(start, end)
124 * clean & invalidate data cache in the range
129 ENTRY(__asm_flush_dcache_range)
134 lsl x2, x2, x3 /* cache line size */
136 /* x2 <- minimal cache line size in cache system */
139 1: dc civac, x0 /* clean & invalidate data or unified cache */
145 ENDPROC(__asm_flush_dcache_range)
148 * void __asm_invalidate_icache_all(void)
150 * invalidate all tlb entries.
152 ENTRY(__asm_invalidate_icache_all)
156 ENDPROC(__asm_invalidate_icache_all)
158 ENTRY(__asm_flush_l3_cache)
159 mov x0, #0 /* return status as success */
161 ENDPROC(__asm_flush_l3_cache)
162 .weak __asm_flush_l3_cache