3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/armv8/mmu.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 #ifndef CONFIG_SYS_DCACHE_OFF
15 void set_pgtable_section(u64 *page_table, u64 index, u64 section,
20 value = section | PMD_TYPE_SECT | PMD_SECT_AF;
21 value |= PMD_ATTRINDX(memory_type);
22 page_table[index] = value;
25 /* to activate the MMU we need to set up virtual memory */
26 static void mmu_setup(void)
29 u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
32 /* Setup an identity-mapping for all spaces */
33 for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
34 set_pgtable_section(page_table, i, i << SECTION_SHIFT,
38 /* Setup an identity-mapping for all RAM space */
39 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
40 ulong start = bd->bi_dram[i].start;
41 ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
42 for (j = start >> SECTION_SHIFT;
43 j < end >> SECTION_SHIFT; j++) {
44 set_pgtable_section(page_table, j, j << SECTION_SHIFT,
52 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
53 TCR_FLAGS | TCR_EL1_IPS_BITS,
56 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
57 TCR_FLAGS | TCR_EL2_IPS_BITS,
60 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
61 TCR_FLAGS | TCR_EL3_IPS_BITS,
65 set_sctlr(get_sctlr() | CR_M);
69 * Performs a invalidation of the entire data cache at all levels
71 void invalidate_dcache_all(void)
73 __asm_invalidate_dcache_all();
77 * Performs a clean & invalidation of the entire data cache at all levels.
78 * This function needs to be inline to avoid using stack.
79 * __asm_flush_l3_cache return status of timeout
81 inline void flush_dcache_all(void)
85 __asm_flush_dcache_all();
86 ret = __asm_flush_l3_cache();
88 debug("flushing dcache returns 0x%x\n", ret);
90 debug("flushing dcache successfully.\n");
94 * Invalidates range in all levels of D-cache/unified cache
96 void invalidate_dcache_range(unsigned long start, unsigned long stop)
98 __asm_flush_dcache_range(start, stop);
102 * Flush range(clean & invalidate) from all levels of D-cache/unified cache
104 void flush_dcache_range(unsigned long start, unsigned long stop)
106 __asm_flush_dcache_range(start, stop);
109 void dcache_enable(void)
111 /* The data cache is not active unless the mmu is enabled */
112 if (!(get_sctlr() & CR_M)) {
113 invalidate_dcache_all();
114 __asm_invalidate_tlb_all();
118 set_sctlr(get_sctlr() | CR_C);
121 void dcache_disable(void)
127 /* if cache isn't enabled no need to disable */
131 set_sctlr(sctlr & ~(CR_C|CR_M));
134 __asm_invalidate_tlb_all();
137 int dcache_status(void)
139 return (get_sctlr() & CR_C) != 0;
142 u64 *__weak arch_get_page_table(void) {
143 puts("No page table offset defined\n");
148 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
149 enum dcache_option option)
151 u64 *page_table = arch_get_page_table();
154 if (page_table == NULL)
157 end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
159 start = start >> MMU_SECTION_SHIFT;
160 for (upto = start; upto < end; upto++) {
161 page_table[upto] &= ~PMD_ATTRINDX_MASK;
162 page_table[upto] |= PMD_ATTRINDX(option);
164 asm volatile("dsb sy");
165 __asm_invalidate_tlb_all();
166 asm volatile("dsb sy");
168 start = start << MMU_SECTION_SHIFT;
169 end = end << MMU_SECTION_SHIFT;
170 flush_dcache_range(start, end);
171 asm volatile("dsb sy");
173 #else /* CONFIG_SYS_DCACHE_OFF */
175 void invalidate_dcache_all(void)
179 void flush_dcache_all(void)
183 void dcache_enable(void)
187 void dcache_disable(void)
191 int dcache_status(void)
196 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
197 enum dcache_option option)
201 #endif /* CONFIG_SYS_DCACHE_OFF */
203 #ifndef CONFIG_SYS_ICACHE_OFF
205 void icache_enable(void)
207 __asm_invalidate_icache_all();
208 set_sctlr(get_sctlr() | CR_I);
211 void icache_disable(void)
213 set_sctlr(get_sctlr() & ~CR_I);
216 int icache_status(void)
218 return (get_sctlr() & CR_I) != 0;
221 void invalidate_icache_all(void)
223 __asm_invalidate_icache_all();
226 #else /* CONFIG_SYS_ICACHE_OFF */
228 void icache_enable(void)
232 void icache_disable(void)
236 int icache_status(void)
241 void invalidate_icache_all(void)
245 #endif /* CONFIG_SYS_ICACHE_OFF */
248 * Enable dCache & iCache, whether cache is actually enabled
249 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
251 void __weak enable_caches(void)