3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/armv8/mmu.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 #ifndef CONFIG_SYS_DCACHE_OFF
16 static void set_pgtable_section(u64 section, u64 memory_type)
18 u64 *page_table = (u64 *)gd->arch.tlb_addr;
21 value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
22 value |= PMD_ATTRINDX(memory_type);
23 page_table[section] = value;
26 /* to activate the MMU we need to set up virtual memory */
27 static void mmu_setup(void)
32 /* Setup an identity-mapping for all spaces */
33 for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
34 set_pgtable_section(i, MT_DEVICE_NGNRNE);
36 /* Setup an identity-mapping for all RAM space */
37 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
38 ulong start = bd->bi_dram[i].start;
39 ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
40 for (j = start >> SECTION_SHIFT;
41 j < end >> SECTION_SHIFT; j++) {
42 set_pgtable_section(j, MT_NORMAL);
49 asm volatile("msr ttbr0_el1, %0"
50 : : "r" (gd->arch.tlb_addr) : "memory");
51 asm volatile("msr tcr_el1, %0"
52 : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
54 asm volatile("msr mair_el1, %0"
55 : : "r" (MEMORY_ATTRIBUTES) : "memory");
57 asm volatile("msr ttbr0_el2, %0"
58 : : "r" (gd->arch.tlb_addr) : "memory");
59 asm volatile("msr tcr_el2, %0"
60 : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
62 asm volatile("msr mair_el2, %0"
63 : : "r" (MEMORY_ATTRIBUTES) : "memory");
65 asm volatile("msr ttbr0_el3, %0"
66 : : "r" (gd->arch.tlb_addr) : "memory");
67 asm volatile("msr tcr_el3, %0"
68 : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
70 asm volatile("msr mair_el3, %0"
71 : : "r" (MEMORY_ATTRIBUTES) : "memory");
75 set_sctlr(get_sctlr() | CR_M);
79 * Performs a invalidation of the entire data cache at all levels
81 void invalidate_dcache_all(void)
83 __asm_invalidate_dcache_all();
87 * Performs a clean & invalidation of the entire data cache at all levels
89 void flush_dcache_all(void)
91 __asm_flush_dcache_all();
95 * Invalidates range in all levels of D-cache/unified cache
97 void invalidate_dcache_range(unsigned long start, unsigned long stop)
99 __asm_flush_dcache_range(start, stop);
103 * Flush range(clean & invalidate) from all levels of D-cache/unified cache
105 void flush_dcache_range(unsigned long start, unsigned long stop)
107 __asm_flush_dcache_range(start, stop);
110 void dcache_enable(void)
112 /* The data cache is not active unless the mmu is enabled */
113 if (!(get_sctlr() & CR_M)) {
114 invalidate_dcache_all();
115 __asm_invalidate_tlb_all();
119 set_sctlr(get_sctlr() | CR_C);
122 void dcache_disable(void)
128 /* if cache isn't enabled no need to disable */
132 set_sctlr(sctlr & ~(CR_C|CR_M));
135 __asm_invalidate_tlb_all();
138 int dcache_status(void)
140 return (get_sctlr() & CR_C) != 0;
143 #else /* CONFIG_SYS_DCACHE_OFF */
145 void invalidate_dcache_all(void)
149 void flush_dcache_all(void)
153 void invalidate_dcache_range(unsigned long start, unsigned long stop)
157 void flush_dcache_range(unsigned long start, unsigned long stop)
161 void dcache_enable(void)
165 void dcache_disable(void)
169 int dcache_status(void)
174 #endif /* CONFIG_SYS_DCACHE_OFF */
176 #ifndef CONFIG_SYS_ICACHE_OFF
178 void icache_enable(void)
180 __asm_invalidate_icache_all();
181 set_sctlr(get_sctlr() | CR_I);
184 void icache_disable(void)
186 set_sctlr(get_sctlr() & ~CR_I);
189 int icache_status(void)
191 return (get_sctlr() & CR_I) != 0;
194 void invalidate_icache_all(void)
196 __asm_invalidate_icache_all();
199 #else /* CONFIG_SYS_ICACHE_OFF */
201 void icache_enable(void)
205 void icache_disable(void)
209 int icache_status(void)
214 void invalidate_icache_all(void)
218 #endif /* CONFIG_SYS_ICACHE_OFF */
221 * Enable dCache & iCache, whether cache is actually enabled
222 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
224 void enable_caches(void)
231 * Flush range from all levels of d-cache/unified-cache
233 void flush_cache(unsigned long start, unsigned long size)
235 flush_dcache_range(start, start + size);