7 select SYS_FSL_ERRATUM_A010315
11 select ARMV8_SET_SMPEN
15 select SYS_FSL_DDR_VER_50
16 select SYS_FSL_ERRATUM_A008850
17 select SYS_FSL_ERRATUM_A009660
18 select SYS_FSL_ERRATUM_A009663
19 select SYS_FSL_ERRATUM_A009929
20 select SYS_FSL_ERRATUM_A009942
21 select SYS_FSL_ERRATUM_A010315
22 select SYS_FSL_ERRATUM_A010539
23 select SYS_FSL_HAS_DDR3
24 select SYS_FSL_HAS_DDR4
28 select ARMV8_SET_SMPEN
32 select SYS_FSL_DDR_VER_50
33 select SYS_FSL_ERRATUM_A008511
34 select SYS_FSL_ERRATUM_A009801
35 select SYS_FSL_ERRATUM_A009803
36 select SYS_FSL_ERRATUM_A009942
37 select SYS_FSL_ERRATUM_A010165
38 select SYS_FSL_ERRATUM_A010539
39 select SYS_FSL_HAS_DDR4
44 select ARMV8_SET_SMPEN
48 select SYS_FSL_DDR_VER_50
49 select SYS_FSL_HAS_DP_DDR
50 select SYS_FSL_HAS_SEC
51 select SYS_FSL_HAS_DDR4
52 select SYS_FSL_SEC_COMPAT_5
55 select SYS_FSL_ERRATUM_A008336
56 select SYS_FSL_ERRATUM_A008511
57 select SYS_FSL_ERRATUM_A008514
58 select SYS_FSL_ERRATUM_A008585
59 select SYS_FSL_ERRATUM_A009635
60 select SYS_FSL_ERRATUM_A009663
61 select SYS_FSL_ERRATUM_A009801
62 select SYS_FSL_ERRATUM_A009803
63 select SYS_FSL_ERRATUM_A009942
64 select SYS_FSL_ERRATUM_A010165
68 select SYS_FSL_HAS_SEC
69 select SYS_FSL_SEC_COMPAT_5
79 menu "Layerscape architecture"
80 depends on FSL_LSCH2 || FSL_LSCH3
82 config FSL_PCIE_COMPAT
83 string "PCIe compatible of Kernel DT"
84 depends on PCIE_LAYERSCAPE
85 default "fsl,ls1012a-pcie" if ARCH_LS1012A
86 default "fsl,ls1043a-pcie" if ARCH_LS1043A
87 default "fsl,ls1046a-pcie" if ARCH_LS1046A
88 default "fsl,ls2080a-pcie" if ARCH_LS2080A
90 This compatible is used to find pci controller node in Kernel DT
93 config HAS_FEATURE_GIC64K_ALIGN
95 default y if ARCH_LS1043A
97 config HAS_FEATURE_ENHANCED_MSI
99 default y if ARCH_LS1043A
101 menu "Layerscape PPA"
103 bool "FSL Layerscape PPA firmware support"
104 depends on !ARMV8_PSCI
105 depends on ARCH_LS1043A || ARCH_LS1046A
106 select SEC_FIRMWARE_ARMV8_PSCI
108 The FSL Primary Protected Application (PPA) is a software component
109 which is loaded during boot stage, and then remains resident in RAM
110 and runs in the TrustZone after boot.
114 config SYS_FSL_ERRATUM_A010315
115 bool "Workaround for PCIe erratum A010315"
117 config SYS_FSL_ERRATUM_A010539
118 bool "Workaround for PIN MUX erratum A010539"
121 int "Maximum number of CPUs permitted for Layerscape"
122 default 4 if ARCH_LS1043A
123 default 4 if ARCH_LS1046A
124 default 16 if ARCH_LS2080A
127 Set this number to the maximum number of possible CPUs in the SoC.
128 SoCs may have multiple clusters with each cluster may have multiple
129 ports. If some ports are reserved but higher ports are used for
130 cores, count the reserved ports. This will allocate enough memory
131 in spin table to properly handle all cores.
136 Enable Freescale Secure Boot feature
139 bool "Init the QSPI AHB bus"
141 The default setting for QSPI AHB bus just support 3bytes addressing.
142 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
143 bus for those flashes to support the full QSPI flash size.
145 config SYS_FSL_IFC_BANK_COUNT
146 int "Maximum banks of Integrated flash controller"
147 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
148 default 4 if ARCH_LS1043A
149 default 4 if ARCH_LS1046A
150 default 8 if ARCH_LS2080A
152 config SYS_FSL_HAS_DP_DDR
155 config SYS_FSL_SRDS_1
158 config SYS_FSL_SRDS_2
161 config SYS_HAS_SERDES
166 menu "Layerscape clock tree configuration"
167 depends on FSL_LSCH2 || FSL_LSCH3
170 bool "Enable clock tree initialization"
173 config CLUSTER_CLK_FREQ
174 int "Reference clock of core cluster"
175 depends on ARCH_LS1012A
178 This number is the reference clock frequency of core PLL.
179 For most platforms, the core PLL and Platform PLL have the same
180 reference clock, but for some platforms, LS1012A for instance,
181 they are provided sepatately.
183 config SYS_FSL_PCLK_DIV
184 int "Platform clock divider"
185 default 1 if ARCH_LS1043A
186 default 1 if ARCH_LS1046A
189 This is the divider that is used to derive Platform clock from
190 Platform PLL, in another word:
191 Platform_clk = Platform_PLL_freq / this_divider
193 config SYS_FSL_DSPI_CLK_DIV
194 int "DSPI clock divider"
195 default 1 if ARCH_LS1043A
198 This is the divider that is used to derive DSPI clock from Platform
199 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
201 config SYS_FSL_DUART_CLK_DIV
202 int "DUART clock divider"
203 default 1 if ARCH_LS1043A
206 This is the divider that is used to derive DUART clock from Platform
207 clock, in another word DUART_clk = Platform_clk / this_divider.
209 config SYS_FSL_I2C_CLK_DIV
210 int "I2C clock divider"
211 default 1 if ARCH_LS1043A
214 This is the divider that is used to derive I2C clock from Platform
215 clock, in another word I2C_clk = Platform_clk / this_divider.
217 config SYS_FSL_IFC_CLK_DIV
218 int "IFC clock divider"
219 default 1 if ARCH_LS1043A
222 This is the divider that is used to derive IFC clock from Platform
223 clock, in another word IFC_clk = Platform_clk / this_divider.
225 config SYS_FSL_LPUART_CLK_DIV
226 int "LPUART clock divider"
227 default 1 if ARCH_LS1043A
230 This is the divider that is used to derive LPUART clock from Platform
231 clock, in another word LPUART_clk = Platform_clk / this_divider.
233 config SYS_FSL_SDHC_CLK_DIV
234 int "SDHC clock divider"
235 default 1 if ARCH_LS1043A
236 default 1 if ARCH_LS1012A
239 This is the divider that is used to derive SDHC clock from Platform
240 clock, in another word SDHC_clk = Platform_clk / this_divider.
243 config SYS_FSL_ERRATUM_A008336
246 config SYS_FSL_ERRATUM_A008514
249 config SYS_FSL_ERRATUM_A008585
252 config SYS_FSL_ERRATUM_A008850
255 config SYS_FSL_ERRATUM_A009635
258 config SYS_FSL_ERRATUM_A009660
261 config SYS_FSL_ERRATUM_A009929