7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A008850
40 select SYS_FSL_ERRATUM_A009801
41 select SYS_FSL_ERRATUM_A009803
42 select SYS_FSL_ERRATUM_A009942
43 select SYS_FSL_ERRATUM_A010165
44 select SYS_FSL_ERRATUM_A010539
45 select SYS_FSL_HAS_DDR4
47 select ARCH_EARLY_INIT_R
48 select BOARD_EARLY_INIT_F
52 select ARMV8_SET_SMPEN
53 select ARM_ERRATA_826974
54 select ARM_ERRATA_828024
55 select ARM_ERRATA_829520
56 select ARM_ERRATA_833471
60 select SYS_FSL_DDR_VER_50
61 select SYS_FSL_HAS_DP_DDR
62 select SYS_FSL_HAS_SEC
63 select SYS_FSL_HAS_DDR4
64 select SYS_FSL_SEC_COMPAT_5
69 select SYS_FSL_ERRATUM_A008336
70 select SYS_FSL_ERRATUM_A008511
71 select SYS_FSL_ERRATUM_A008514
72 select SYS_FSL_ERRATUM_A008585
73 select SYS_FSL_ERRATUM_A009635
74 select SYS_FSL_ERRATUM_A009663
75 select SYS_FSL_ERRATUM_A009801
76 select SYS_FSL_ERRATUM_A009803
77 select SYS_FSL_ERRATUM_A009942
78 select SYS_FSL_ERRATUM_A010165
79 select SYS_FSL_ERRATUM_A009203
80 select ARCH_EARLY_INIT_R
81 select BOARD_EARLY_INIT_F
85 select SYS_FSL_HAS_SEC
86 select SYS_FSL_SEC_COMPAT_5
97 bool "Management Complex network"
98 depends on ARCH_LS2080A
102 Enable Management Complex (MC) network
104 menu "Layerscape architecture"
105 depends on FSL_LSCH2 || FSL_LSCH3
107 config FSL_PCIE_COMPAT
108 string "PCIe compatible of Kernel DT"
109 depends on PCIE_LAYERSCAPE
110 default "fsl,ls1012a-pcie" if ARCH_LS1012A
111 default "fsl,ls1043a-pcie" if ARCH_LS1043A
112 default "fsl,ls1046a-pcie" if ARCH_LS1046A
113 default "fsl,ls2080a-pcie" if ARCH_LS2080A
115 This compatible is used to find pci controller node in Kernel DT
118 config HAS_FEATURE_GIC64K_ALIGN
120 default y if ARCH_LS1043A
122 config HAS_FEATURE_ENHANCED_MSI
124 default y if ARCH_LS1043A
126 menu "Layerscape PPA"
128 bool "FSL Layerscape PPA firmware support"
129 depends on !ARMV8_PSCI
130 select ARMV8_SEC_FIRMWARE_SUPPORT
131 select SEC_FIRMWARE_ARMV8_PSCI
132 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
134 The FSL Primary Protected Application (PPA) is a software component
135 which is loaded during boot stage, and then remains resident in RAM
136 and runs in the TrustZone after boot.
139 prompt "FSL Layerscape PPA firmware loading-media select"
140 depends on FSL_LS_PPA
141 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
142 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
143 default SYS_LS_PPA_FW_IN_XIP
145 config SYS_LS_PPA_FW_IN_XIP
148 Say Y here if the PPA firmware locate at XIP flash, such
149 as NOR or QSPI flash.
151 config SYS_LS_PPA_FW_IN_MMC
152 bool "eMMC or SD Card"
154 Say Y here if the PPA firmware locate at eMMC/SD card.
156 config SYS_LS_PPA_FW_IN_NAND
159 Say Y here if the PPA firmware locate at NAND flash.
163 config SYS_LS_PPA_FW_ADDR
164 hex "Address of PPA firmware loading from"
165 depends on FSL_LS_PPA
166 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
167 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
168 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
169 default 0x500000 if SYS_LS_PPA_FW_IN_MMC
170 default 0x500000 if SYS_LS_PPA_FW_IN_NAND
173 If the PPA firmware locate at XIP flash, such as NOR or
174 QSPI flash, this address is a directly memory-mapped.
175 If it is in a serial accessed flash, such as NAND and SD
176 card, it is a byte offset.
178 config SYS_LS_PPA_ESBC_ADDR
179 hex "hdr address of PPA firmware loading from"
180 depends on FSL_LS_PPA && CHAIN_OF_TRUST
181 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
182 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
183 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
184 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
186 If the PPA header firmware locate at XIP flash, such as NOR or
187 QSPI flash, this address is a directly memory-mapped.
188 If it is in a serial accessed flash, such as NAND and SD
189 card, it is a byte offset.
193 config SYS_FSL_ERRATUM_A010315
194 bool "Workaround for PCIe erratum A010315"
196 config SYS_FSL_ERRATUM_A010539
197 bool "Workaround for PIN MUX erratum A010539"
200 int "Maximum number of CPUs permitted for Layerscape"
201 default 4 if ARCH_LS1043A
202 default 4 if ARCH_LS1046A
203 default 16 if ARCH_LS2080A
206 Set this number to the maximum number of possible CPUs in the SoC.
207 SoCs may have multiple clusters with each cluster may have multiple
208 ports. If some ports are reserved but higher ports are used for
209 cores, count the reserved ports. This will allocate enough memory
210 in spin table to properly handle all cores.
215 Enable Freescale Secure Boot feature
218 bool "Init the QSPI AHB bus"
220 The default setting for QSPI AHB bus just support 3bytes addressing.
221 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
222 bus for those flashes to support the full QSPI flash size.
224 config SYS_FSL_IFC_BANK_COUNT
225 int "Maximum banks of Integrated flash controller"
226 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
227 default 4 if ARCH_LS1043A
228 default 4 if ARCH_LS1046A
229 default 8 if ARCH_LS2080A
231 config SYS_FSL_HAS_DP_DDR
234 config SYS_FSL_SRDS_1
237 config SYS_FSL_SRDS_2
240 config SYS_HAS_SERDES
251 menu "Layerscape clock tree configuration"
252 depends on FSL_LSCH2 || FSL_LSCH3
255 bool "Enable clock tree initialization"
258 config CLUSTER_CLK_FREQ
259 int "Reference clock of core cluster"
260 depends on ARCH_LS1012A
263 This number is the reference clock frequency of core PLL.
264 For most platforms, the core PLL and Platform PLL have the same
265 reference clock, but for some platforms, LS1012A for instance,
266 they are provided sepatately.
268 config SYS_FSL_PCLK_DIV
269 int "Platform clock divider"
270 default 1 if ARCH_LS1043A
271 default 1 if ARCH_LS1046A
274 This is the divider that is used to derive Platform clock from
275 Platform PLL, in another word:
276 Platform_clk = Platform_PLL_freq / this_divider
278 config SYS_FSL_DSPI_CLK_DIV
279 int "DSPI clock divider"
280 default 1 if ARCH_LS1043A
283 This is the divider that is used to derive DSPI clock from Platform
284 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
286 config SYS_FSL_DUART_CLK_DIV
287 int "DUART clock divider"
288 default 1 if ARCH_LS1043A
291 This is the divider that is used to derive DUART clock from Platform
292 clock, in another word DUART_clk = Platform_clk / this_divider.
294 config SYS_FSL_I2C_CLK_DIV
295 int "I2C clock divider"
296 default 1 if ARCH_LS1043A
299 This is the divider that is used to derive I2C clock from Platform
300 clock, in another word I2C_clk = Platform_clk / this_divider.
302 config SYS_FSL_IFC_CLK_DIV
303 int "IFC clock divider"
304 default 1 if ARCH_LS1043A
307 This is the divider that is used to derive IFC clock from Platform
308 clock, in another word IFC_clk = Platform_clk / this_divider.
310 config SYS_FSL_LPUART_CLK_DIV
311 int "LPUART clock divider"
312 default 1 if ARCH_LS1043A
315 This is the divider that is used to derive LPUART clock from Platform
316 clock, in another word LPUART_clk = Platform_clk / this_divider.
318 config SYS_FSL_SDHC_CLK_DIV
319 int "SDHC clock divider"
320 default 1 if ARCH_LS1043A
321 default 1 if ARCH_LS1012A
324 This is the divider that is used to derive SDHC clock from Platform
325 clock, in another word SDHC_clk = Platform_clk / this_divider.
331 Reserve memory from the top, tracked by gd->arch.resv_ram. This
332 reserved RAM can be used by special driver that resides in memory
333 after U-Boot exits. It's up to implementation to allocate and allow
334 access to this reserved memory. For example, the reserved RAM can
335 be at the high end of physical memory. The reserve RAM may be
336 excluded from memory bank(s) passed to OS, or marked as reserved.
338 config SYS_FSL_ERRATUM_A008336
341 config SYS_FSL_ERRATUM_A008514
344 config SYS_FSL_ERRATUM_A008585
347 config SYS_FSL_ERRATUM_A008850
350 config SYS_FSL_ERRATUM_A009203
353 config SYS_FSL_ERRATUM_A009635
356 config SYS_FSL_ERRATUM_A009660
359 config SYS_FSL_ERRATUM_A009929
362 config SYS_MC_RSV_MEM_ALIGN
363 hex "Management Complex reserved memory alignment"
367 Reserved memory needs to be aligned for MC to use. Default value