7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A008850
40 select SYS_FSL_ERRATUM_A009801
41 select SYS_FSL_ERRATUM_A009803
42 select SYS_FSL_ERRATUM_A009942
43 select SYS_FSL_ERRATUM_A010165
44 select SYS_FSL_ERRATUM_A010539
45 select SYS_FSL_HAS_DDR4
47 select ARCH_EARLY_INIT_R
48 select BOARD_EARLY_INIT_F
52 select ARMV8_SET_SMPEN
53 select ARM_ERRATA_826974
54 select ARM_ERRATA_828024
55 select ARM_ERRATA_829520
56 select ARM_ERRATA_833471
60 select SYS_FSL_DDR_VER_50
61 select SYS_FSL_HAS_DP_DDR
62 select SYS_FSL_HAS_SEC
63 select SYS_FSL_HAS_DDR4
64 select SYS_FSL_SEC_COMPAT_5
67 select SYS_FSL_ERRATUM_A008336
68 select SYS_FSL_ERRATUM_A008511
69 select SYS_FSL_ERRATUM_A008514
70 select SYS_FSL_ERRATUM_A008585
71 select SYS_FSL_ERRATUM_A009635
72 select SYS_FSL_ERRATUM_A009663
73 select SYS_FSL_ERRATUM_A009801
74 select SYS_FSL_ERRATUM_A009803
75 select SYS_FSL_ERRATUM_A009942
76 select SYS_FSL_ERRATUM_A010165
77 select SYS_FSL_ERRATUM_A009203
78 select ARCH_EARLY_INIT_R
79 select BOARD_EARLY_INIT_F
83 select SYS_FSL_HAS_SEC
84 select SYS_FSL_SEC_COMPAT_5
95 bool "Management Complex network"
96 depends on ARCH_LS2080A
100 Enable Management Complex (MC) network
102 menu "Layerscape architecture"
103 depends on FSL_LSCH2 || FSL_LSCH3
105 config FSL_PCIE_COMPAT
106 string "PCIe compatible of Kernel DT"
107 depends on PCIE_LAYERSCAPE
108 default "fsl,ls1012a-pcie" if ARCH_LS1012A
109 default "fsl,ls1043a-pcie" if ARCH_LS1043A
110 default "fsl,ls1046a-pcie" if ARCH_LS1046A
111 default "fsl,ls2080a-pcie" if ARCH_LS2080A
113 This compatible is used to find pci controller node in Kernel DT
116 config HAS_FEATURE_GIC64K_ALIGN
118 default y if ARCH_LS1043A
120 config HAS_FEATURE_ENHANCED_MSI
122 default y if ARCH_LS1043A
124 menu "Layerscape PPA"
126 bool "FSL Layerscape PPA firmware support"
127 depends on !ARMV8_PSCI
128 select ARMV8_SEC_FIRMWARE_SUPPORT
129 select SEC_FIRMWARE_ARMV8_PSCI
130 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
132 The FSL Primary Protected Application (PPA) is a software component
133 which is loaded during boot stage, and then remains resident in RAM
134 and runs in the TrustZone after boot.
137 prompt "FSL Layerscape PPA firmware loading-media select"
138 depends on FSL_LS_PPA
139 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
140 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
141 default SYS_LS_PPA_FW_IN_XIP
143 config SYS_LS_PPA_FW_IN_XIP
146 Say Y here if the PPA firmware locate at XIP flash, such
147 as NOR or QSPI flash.
149 config SYS_LS_PPA_FW_IN_MMC
150 bool "eMMC or SD Card"
152 Say Y here if the PPA firmware locate at eMMC/SD card.
154 config SYS_LS_PPA_FW_IN_NAND
157 Say Y here if the PPA firmware locate at NAND flash.
161 config SYS_LS_PPA_FW_ADDR
162 hex "Address of PPA firmware loading from"
163 depends on FSL_LS_PPA
164 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
165 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
166 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
167 default 0x500000 if SYS_LS_PPA_FW_IN_MMC
168 default 0x500000 if SYS_LS_PPA_FW_IN_NAND
171 If the PPA firmware locate at XIP flash, such as NOR or
172 QSPI flash, this address is a directly memory-mapped.
173 If it is in a serial accessed flash, such as NAND and SD
174 card, it is a byte offset.
176 config SYS_LS_PPA_ESBC_ADDR
177 hex "hdr address of PPA firmware loading from"
178 depends on FSL_LS_PPA && CHAIN_OF_TRUST
179 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
180 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
181 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
182 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
184 If the PPA header firmware locate at XIP flash, such as NOR or
185 QSPI flash, this address is a directly memory-mapped.
186 If it is in a serial accessed flash, such as NAND and SD
187 card, it is a byte offset.
191 config SYS_FSL_ERRATUM_A010315
192 bool "Workaround for PCIe erratum A010315"
194 config SYS_FSL_ERRATUM_A010539
195 bool "Workaround for PIN MUX erratum A010539"
198 int "Maximum number of CPUs permitted for Layerscape"
199 default 4 if ARCH_LS1043A
200 default 4 if ARCH_LS1046A
201 default 16 if ARCH_LS2080A
204 Set this number to the maximum number of possible CPUs in the SoC.
205 SoCs may have multiple clusters with each cluster may have multiple
206 ports. If some ports are reserved but higher ports are used for
207 cores, count the reserved ports. This will allocate enough memory
208 in spin table to properly handle all cores.
213 Enable Freescale Secure Boot feature
216 bool "Init the QSPI AHB bus"
218 The default setting for QSPI AHB bus just support 3bytes addressing.
219 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
220 bus for those flashes to support the full QSPI flash size.
222 config SYS_FSL_IFC_BANK_COUNT
223 int "Maximum banks of Integrated flash controller"
224 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
225 default 4 if ARCH_LS1043A
226 default 4 if ARCH_LS1046A
227 default 8 if ARCH_LS2080A
229 config SYS_FSL_HAS_DP_DDR
232 config SYS_FSL_SRDS_1
235 config SYS_FSL_SRDS_2
238 config SYS_HAS_SERDES
243 menu "Layerscape clock tree configuration"
244 depends on FSL_LSCH2 || FSL_LSCH3
247 bool "Enable clock tree initialization"
250 config CLUSTER_CLK_FREQ
251 int "Reference clock of core cluster"
252 depends on ARCH_LS1012A
255 This number is the reference clock frequency of core PLL.
256 For most platforms, the core PLL and Platform PLL have the same
257 reference clock, but for some platforms, LS1012A for instance,
258 they are provided sepatately.
260 config SYS_FSL_PCLK_DIV
261 int "Platform clock divider"
262 default 1 if ARCH_LS1043A
263 default 1 if ARCH_LS1046A
266 This is the divider that is used to derive Platform clock from
267 Platform PLL, in another word:
268 Platform_clk = Platform_PLL_freq / this_divider
270 config SYS_FSL_DSPI_CLK_DIV
271 int "DSPI clock divider"
272 default 1 if ARCH_LS1043A
275 This is the divider that is used to derive DSPI clock from Platform
276 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
278 config SYS_FSL_DUART_CLK_DIV
279 int "DUART clock divider"
280 default 1 if ARCH_LS1043A
283 This is the divider that is used to derive DUART clock from Platform
284 clock, in another word DUART_clk = Platform_clk / this_divider.
286 config SYS_FSL_I2C_CLK_DIV
287 int "I2C clock divider"
288 default 1 if ARCH_LS1043A
291 This is the divider that is used to derive I2C clock from Platform
292 clock, in another word I2C_clk = Platform_clk / this_divider.
294 config SYS_FSL_IFC_CLK_DIV
295 int "IFC clock divider"
296 default 1 if ARCH_LS1043A
299 This is the divider that is used to derive IFC clock from Platform
300 clock, in another word IFC_clk = Platform_clk / this_divider.
302 config SYS_FSL_LPUART_CLK_DIV
303 int "LPUART clock divider"
304 default 1 if ARCH_LS1043A
307 This is the divider that is used to derive LPUART clock from Platform
308 clock, in another word LPUART_clk = Platform_clk / this_divider.
310 config SYS_FSL_SDHC_CLK_DIV
311 int "SDHC clock divider"
312 default 1 if ARCH_LS1043A
313 default 1 if ARCH_LS1012A
316 This is the divider that is used to derive SDHC clock from Platform
317 clock, in another word SDHC_clk = Platform_clk / this_divider.
323 Reserve memory from the top, tracked by gd->arch.resv_ram. This
324 reserved RAM can be used by special driver that resides in memory
325 after U-Boot exits. It's up to implementation to allocate and allow
326 access to this reserved memory. For example, the reserved RAM can
327 be at the high end of physical memory. The reserve RAM may be
328 excluded from memory bank(s) passed to OS, or marked as reserved.
330 config SYS_FSL_ERRATUM_A008336
333 config SYS_FSL_ERRATUM_A008514
336 config SYS_FSL_ERRATUM_A008585
339 config SYS_FSL_ERRATUM_A008850
342 config SYS_FSL_ERRATUM_A009203
345 config SYS_FSL_ERRATUM_A009635
348 config SYS_FSL_ERRATUM_A009660
351 config SYS_FSL_ERRATUM_A009929
354 config SYS_MC_RSV_MEM_ALIGN
355 hex "Management Complex reserved memory alignment"
359 Reserved memory needs to be aligned for MC to use. Default value