7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008511
38 select SYS_FSL_ERRATUM_A009801
39 select SYS_FSL_ERRATUM_A009803
40 select SYS_FSL_ERRATUM_A009942
41 select SYS_FSL_ERRATUM_A010165
42 select SYS_FSL_ERRATUM_A010539
43 select SYS_FSL_HAS_DDR4
45 select ARCH_EARLY_INIT_R
46 select BOARD_EARLY_INIT_F
50 select ARMV8_SET_SMPEN
54 select SYS_FSL_DDR_VER_50
55 select SYS_FSL_HAS_DP_DDR
56 select SYS_FSL_HAS_SEC
57 select SYS_FSL_HAS_DDR4
58 select SYS_FSL_SEC_COMPAT_5
61 select SYS_FSL_ERRATUM_A008336
62 select SYS_FSL_ERRATUM_A008511
63 select SYS_FSL_ERRATUM_A008514
64 select SYS_FSL_ERRATUM_A008585
65 select SYS_FSL_ERRATUM_A009635
66 select SYS_FSL_ERRATUM_A009663
67 select SYS_FSL_ERRATUM_A009801
68 select SYS_FSL_ERRATUM_A009803
69 select SYS_FSL_ERRATUM_A009942
70 select SYS_FSL_ERRATUM_A010165
71 select ARCH_EARLY_INIT_R
72 select BOARD_EARLY_INIT_F
76 select SYS_FSL_HAS_SEC
77 select SYS_FSL_SEC_COMPAT_5
87 menu "Layerscape architecture"
88 depends on FSL_LSCH2 || FSL_LSCH3
90 config FSL_PCIE_COMPAT
91 string "PCIe compatible of Kernel DT"
92 depends on PCIE_LAYERSCAPE
93 default "fsl,ls1012a-pcie" if ARCH_LS1012A
94 default "fsl,ls1043a-pcie" if ARCH_LS1043A
95 default "fsl,ls1046a-pcie" if ARCH_LS1046A
96 default "fsl,ls2080a-pcie" if ARCH_LS2080A
98 This compatible is used to find pci controller node in Kernel DT
101 config HAS_FEATURE_GIC64K_ALIGN
103 default y if ARCH_LS1043A
105 config HAS_FEATURE_ENHANCED_MSI
107 default y if ARCH_LS1043A
109 menu "Layerscape PPA"
111 bool "FSL Layerscape PPA firmware support"
112 depends on !ARMV8_PSCI
113 select ARMV8_SEC_FIRMWARE_SUPPORT
114 select SEC_FIRMWARE_ARMV8_PSCI
115 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
117 The FSL Primary Protected Application (PPA) is a software component
118 which is loaded during boot stage, and then remains resident in RAM
119 and runs in the TrustZone after boot.
122 prompt "FSL Layerscape PPA firmware loading-media select"
123 depends on FSL_LS_PPA
124 default SYS_LS_PPA_FW_IN_XIP
126 config SYS_LS_PPA_FW_IN_XIP
129 Say Y here if the PPA firmware locate at XIP flash, such
130 as NOR or QSPI flash.
134 config SYS_LS_PPA_FW_ADDR
135 hex "Address of PPA firmware loading from"
136 depends on FSL_LS_PPA
137 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
138 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
140 If the PPA firmware locate at XIP flash, such as NOR or
141 QSPI flash, this address is a directly memory-mapped.
142 If it is in a serial accessed flash, such as NAND and SD
143 card, it is a byte offset.
146 config SYS_FSL_ERRATUM_A010315
147 bool "Workaround for PCIe erratum A010315"
149 config SYS_FSL_ERRATUM_A010539
150 bool "Workaround for PIN MUX erratum A010539"
153 int "Maximum number of CPUs permitted for Layerscape"
154 default 4 if ARCH_LS1043A
155 default 4 if ARCH_LS1046A
156 default 16 if ARCH_LS2080A
159 Set this number to the maximum number of possible CPUs in the SoC.
160 SoCs may have multiple clusters with each cluster may have multiple
161 ports. If some ports are reserved but higher ports are used for
162 cores, count the reserved ports. This will allocate enough memory
163 in spin table to properly handle all cores.
168 Enable Freescale Secure Boot feature
171 bool "Init the QSPI AHB bus"
173 The default setting for QSPI AHB bus just support 3bytes addressing.
174 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
175 bus for those flashes to support the full QSPI flash size.
177 config SYS_FSL_IFC_BANK_COUNT
178 int "Maximum banks of Integrated flash controller"
179 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
180 default 4 if ARCH_LS1043A
181 default 4 if ARCH_LS1046A
182 default 8 if ARCH_LS2080A
184 config SYS_FSL_HAS_DP_DDR
187 config SYS_FSL_SRDS_1
190 config SYS_FSL_SRDS_2
193 config SYS_HAS_SERDES
198 menu "Layerscape clock tree configuration"
199 depends on FSL_LSCH2 || FSL_LSCH3
202 bool "Enable clock tree initialization"
205 config CLUSTER_CLK_FREQ
206 int "Reference clock of core cluster"
207 depends on ARCH_LS1012A
210 This number is the reference clock frequency of core PLL.
211 For most platforms, the core PLL and Platform PLL have the same
212 reference clock, but for some platforms, LS1012A for instance,
213 they are provided sepatately.
215 config SYS_FSL_PCLK_DIV
216 int "Platform clock divider"
217 default 1 if ARCH_LS1043A
218 default 1 if ARCH_LS1046A
221 This is the divider that is used to derive Platform clock from
222 Platform PLL, in another word:
223 Platform_clk = Platform_PLL_freq / this_divider
225 config SYS_FSL_DSPI_CLK_DIV
226 int "DSPI clock divider"
227 default 1 if ARCH_LS1043A
230 This is the divider that is used to derive DSPI clock from Platform
231 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
233 config SYS_FSL_DUART_CLK_DIV
234 int "DUART clock divider"
235 default 1 if ARCH_LS1043A
238 This is the divider that is used to derive DUART clock from Platform
239 clock, in another word DUART_clk = Platform_clk / this_divider.
241 config SYS_FSL_I2C_CLK_DIV
242 int "I2C clock divider"
243 default 1 if ARCH_LS1043A
246 This is the divider that is used to derive I2C clock from Platform
247 clock, in another word I2C_clk = Platform_clk / this_divider.
249 config SYS_FSL_IFC_CLK_DIV
250 int "IFC clock divider"
251 default 1 if ARCH_LS1043A
254 This is the divider that is used to derive IFC clock from Platform
255 clock, in another word IFC_clk = Platform_clk / this_divider.
257 config SYS_FSL_LPUART_CLK_DIV
258 int "LPUART clock divider"
259 default 1 if ARCH_LS1043A
262 This is the divider that is used to derive LPUART clock from Platform
263 clock, in another word LPUART_clk = Platform_clk / this_divider.
265 config SYS_FSL_SDHC_CLK_DIV
266 int "SDHC clock divider"
267 default 1 if ARCH_LS1043A
268 default 1 if ARCH_LS1012A
271 This is the divider that is used to derive SDHC clock from Platform
272 clock, in another word SDHC_clk = Platform_clk / this_divider.
275 config SYS_FSL_ERRATUM_A008336
278 config SYS_FSL_ERRATUM_A008514
281 config SYS_FSL_ERRATUM_A008585
284 config SYS_FSL_ERRATUM_A008850
287 config SYS_FSL_ERRATUM_A009635
290 config SYS_FSL_ERRATUM_A009660
293 config SYS_FSL_ERRATUM_A009929