7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
34 select ARMV8_SET_SMPEN
38 select SYS_FSL_DDR_VER_50
39 select SYS_FSL_ERRATUM_A008336
40 select SYS_FSL_ERRATUM_A008511
41 select SYS_FSL_ERRATUM_A008850
42 select SYS_FSL_ERRATUM_A009801
43 select SYS_FSL_ERRATUM_A009803
44 select SYS_FSL_ERRATUM_A009942
45 select SYS_FSL_ERRATUM_A010165
46 select SYS_FSL_ERRATUM_A010539
47 select SYS_FSL_HAS_DDR4
49 select ARCH_EARLY_INIT_R
50 select BOARD_EARLY_INIT_F
55 select ARMV8_SET_SMPEN
59 select SYS_FSL_DDR_VER_50
60 select SYS_FSL_ERRATUM_A009803
61 select SYS_FSL_ERRATUM_A009942
62 select SYS_FSL_ERRATUM_A010165
63 select SYS_FSL_ERRATUM_A008511
64 select SYS_FSL_ERRATUM_A008850
65 select SYS_FSL_HAS_CCI400
66 select SYS_FSL_HAS_DDR4
67 select SYS_FSL_HAS_SEC
68 select SYS_FSL_SEC_COMPAT_5
73 select ARCH_EARLY_INIT_R
74 select BOARD_EARLY_INIT_F
78 select ARMV8_SET_SMPEN
79 select ARM_ERRATA_826974
80 select ARM_ERRATA_828024
81 select ARM_ERRATA_829520
82 select ARM_ERRATA_833471
86 select SYS_FSL_DDR_VER_50
87 select SYS_FSL_HAS_CCN504
88 select SYS_FSL_HAS_DP_DDR
89 select SYS_FSL_HAS_SEC
90 select SYS_FSL_HAS_DDR4
91 select SYS_FSL_SEC_COMPAT_5
96 select SYS_FSL_ERRATUM_A008336
97 select SYS_FSL_ERRATUM_A008511
98 select SYS_FSL_ERRATUM_A008514
99 select SYS_FSL_ERRATUM_A008585
100 select SYS_FSL_ERRATUM_A009635
101 select SYS_FSL_ERRATUM_A009663
102 select SYS_FSL_ERRATUM_A009801
103 select SYS_FSL_ERRATUM_A009803
104 select SYS_FSL_ERRATUM_A009942
105 select SYS_FSL_ERRATUM_A010165
106 select SYS_FSL_ERRATUM_A009203
107 select ARCH_EARLY_INIT_R
108 select BOARD_EARLY_INIT_F
112 select SYS_FSL_HAS_CCI400
113 select SYS_FSL_HAS_SEC
114 select SYS_FSL_SEC_COMPAT_5
115 select SYS_FSL_SEC_BE
116 select SYS_FSL_SRDS_1
117 select SYS_HAS_SERDES
121 select SYS_FSL_SRDS_1
122 select SYS_HAS_SERDES
125 bool "Management Complex network"
126 depends on ARCH_LS2080A || ARCH_LS1088A
130 Enable Management Complex (MC) network
132 menu "Layerscape architecture"
133 depends on FSL_LSCH2 || FSL_LSCH3
135 config FSL_PCIE_COMPAT
136 string "PCIe compatible of Kernel DT"
137 depends on PCIE_LAYERSCAPE
138 default "fsl,ls1012a-pcie" if ARCH_LS1012A
139 default "fsl,ls1043a-pcie" if ARCH_LS1043A
140 default "fsl,ls1046a-pcie" if ARCH_LS1046A
141 default "fsl,ls2080a-pcie" if ARCH_LS2080A
142 default "fsl,ls1088a-pcie" if ARCH_LS1088A
144 This compatible is used to find pci controller node in Kernel DT
147 config HAS_FEATURE_GIC64K_ALIGN
149 default y if ARCH_LS1043A
151 config HAS_FEATURE_ENHANCED_MSI
153 default y if ARCH_LS1043A
155 menu "Layerscape PPA"
157 bool "FSL Layerscape PPA firmware support"
158 depends on !ARMV8_PSCI
159 select ARMV8_SEC_FIRMWARE_SUPPORT
160 select SEC_FIRMWARE_ARMV8_PSCI
161 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
163 The FSL Primary Protected Application (PPA) is a software component
164 which is loaded during boot stage, and then remains resident in RAM
165 and runs in the TrustZone after boot.
168 config SPL_FSL_LS_PPA
169 bool "FSL Layerscape PPA firmware support for SPL build"
170 depends on !ARMV8_PSCI
171 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
172 select SEC_FIRMWARE_ARMV8_PSCI
173 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
175 The FSL Primary Protected Application (PPA) is a software component
176 which is loaded during boot stage, and then remains resident in RAM
177 and runs in the TrustZone after boot. This is to load PPA during SPL
178 stage instead of the RAM version of U-Boot. Once PPA is initialized,
179 the rest of U-Boot (including RAM version) runs at EL2.
181 prompt "FSL Layerscape PPA firmware loading-media select"
182 depends on FSL_LS_PPA
183 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
184 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
185 default SYS_LS_PPA_FW_IN_XIP
187 config SYS_LS_PPA_FW_IN_XIP
190 Say Y here if the PPA firmware locate at XIP flash, such
191 as NOR or QSPI flash.
193 config SYS_LS_PPA_FW_IN_MMC
194 bool "eMMC or SD Card"
196 Say Y here if the PPA firmware locate at eMMC/SD card.
198 config SYS_LS_PPA_FW_IN_NAND
201 Say Y here if the PPA firmware locate at NAND flash.
205 config SYS_LS_PPA_FW_ADDR
206 hex "Address of PPA firmware loading from"
207 depends on FSL_LS_PPA
208 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
209 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
210 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
211 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
212 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
213 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
216 If the PPA firmware locate at XIP flash, such as NOR or
217 QSPI flash, this address is a directly memory-mapped.
218 If it is in a serial accessed flash, such as NAND and SD
219 card, it is a byte offset.
221 config SYS_LS_PPA_ESBC_ADDR
222 hex "hdr address of PPA firmware loading from"
223 depends on FSL_LS_PPA && CHAIN_OF_TRUST
224 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
225 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
226 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
227 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
228 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
229 default 0x680000 if SYS_LS_PPA_FW_IN_MMC
230 default 0x680000 if SYS_LS_PPA_FW_IN_NAND
232 If the PPA header firmware locate at XIP flash, such as NOR or
233 QSPI flash, this address is a directly memory-mapped.
234 If it is in a serial accessed flash, such as NAND and SD
235 card, it is a byte offset.
237 config LS_PPA_ESBC_HDR_SIZE
238 hex "Length of PPA ESBC header"
239 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
242 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
243 NAND to memory to validate PPA image.
247 config SYS_FSL_ERRATUM_A010315
248 bool "Workaround for PCIe erratum A010315"
250 config SYS_FSL_ERRATUM_A010539
251 bool "Workaround for PIN MUX erratum A010539"
254 int "Maximum number of CPUs permitted for Layerscape"
255 default 4 if ARCH_LS1043A
256 default 4 if ARCH_LS1046A
257 default 16 if ARCH_LS2080A
258 default 8 if ARCH_LS1088A
261 Set this number to the maximum number of possible CPUs in the SoC.
262 SoCs may have multiple clusters with each cluster may have multiple
263 ports. If some ports are reserved but higher ports are used for
264 cores, count the reserved ports. This will allocate enough memory
265 in spin table to properly handle all cores.
270 Enable Freescale Secure Boot feature
273 bool "Init the QSPI AHB bus"
275 The default setting for QSPI AHB bus just support 3bytes addressing.
276 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
277 bus for those flashes to support the full QSPI flash size.
279 config SYS_CCI400_OFFSET
280 hex "Offset for CCI400 base"
281 depends on SYS_FSL_HAS_CCI400
282 default 0x3090000 if ARCH_LS1088A
283 default 0x180000 if FSL_LSCH2
285 Offset for CCI400 base
286 CCI400 base addr = CCSRBAR + CCI400_OFFSET
288 config SYS_FSL_IFC_BANK_COUNT
289 int "Maximum banks of Integrated flash controller"
290 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
291 default 4 if ARCH_LS1043A
292 default 4 if ARCH_LS1046A
293 default 8 if ARCH_LS2080A || ARCH_LS1088A
295 config SYS_FSL_HAS_CCI400
298 config SYS_FSL_HAS_CCN504
301 config SYS_FSL_HAS_DP_DDR
304 config SYS_FSL_SRDS_1
307 config SYS_FSL_SRDS_2
310 config SYS_HAS_SERDES
321 menu "Layerscape clock tree configuration"
322 depends on FSL_LSCH2 || FSL_LSCH3
325 bool "Enable clock tree initialization"
328 config CLUSTER_CLK_FREQ
329 int "Reference clock of core cluster"
330 depends on ARCH_LS1012A
333 This number is the reference clock frequency of core PLL.
334 For most platforms, the core PLL and Platform PLL have the same
335 reference clock, but for some platforms, LS1012A for instance,
336 they are provided sepatately.
338 config SYS_FSL_PCLK_DIV
339 int "Platform clock divider"
340 default 1 if ARCH_LS1043A
341 default 1 if ARCH_LS1046A
342 default 1 if ARCH_LS1088A
345 This is the divider that is used to derive Platform clock from
346 Platform PLL, in another word:
347 Platform_clk = Platform_PLL_freq / this_divider
349 config SYS_FSL_DSPI_CLK_DIV
350 int "DSPI clock divider"
351 default 1 if ARCH_LS1043A
354 This is the divider that is used to derive DSPI clock from Platform
355 clock, in another word DSPI_clk = Platform_clk / this_divider.
357 config SYS_FSL_DUART_CLK_DIV
358 int "DUART clock divider"
359 default 1 if ARCH_LS1043A
362 This is the divider that is used to derive DUART clock from Platform
363 clock, in another word DUART_clk = Platform_clk / this_divider.
365 config SYS_FSL_I2C_CLK_DIV
366 int "I2C clock divider"
367 default 1 if ARCH_LS1043A
370 This is the divider that is used to derive I2C clock from Platform
371 clock, in another word I2C_clk = Platform_clk / this_divider.
373 config SYS_FSL_IFC_CLK_DIV
374 int "IFC clock divider"
375 default 1 if ARCH_LS1043A
378 This is the divider that is used to derive IFC clock from Platform
379 clock, in another word IFC_clk = Platform_clk / this_divider.
381 config SYS_FSL_LPUART_CLK_DIV
382 int "LPUART clock divider"
383 default 1 if ARCH_LS1043A
386 This is the divider that is used to derive LPUART clock from Platform
387 clock, in another word LPUART_clk = Platform_clk / this_divider.
389 config SYS_FSL_SDHC_CLK_DIV
390 int "SDHC clock divider"
391 default 1 if ARCH_LS1043A
392 default 1 if ARCH_LS1012A
395 This is the divider that is used to derive SDHC clock from Platform
396 clock, in another word SDHC_clk = Platform_clk / this_divider.
402 Reserve memory from the top, tracked by gd->arch.resv_ram. This
403 reserved RAM can be used by special driver that resides in memory
404 after U-Boot exits. It's up to implementation to allocate and allow
405 access to this reserved memory. For example, the reserved RAM can
406 be at the high end of physical memory. The reserve RAM may be
407 excluded from memory bank(s) passed to OS, or marked as reserved.
409 config SYS_FSL_ERRATUM_A008336
412 config SYS_FSL_ERRATUM_A008514
415 config SYS_FSL_ERRATUM_A008585
418 config SYS_FSL_ERRATUM_A008850
421 config SYS_FSL_ERRATUM_A009203
424 config SYS_FSL_ERRATUM_A009635
427 config SYS_FSL_ERRATUM_A009660
430 config SYS_FSL_ERRATUM_A009929
433 config SYS_MC_RSV_MEM_ALIGN
434 hex "Management Complex reserved memory alignment"
436 default 0x20000000 if ARCH_LS2080A
437 default 0x70000000 if ARCH_LS1088A
439 Reserved memory needs to be aligned for MC to use. Default value
443 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A