7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A008997
20 select SYS_FSL_ERRATUM_A009007
21 select SYS_FSL_ERRATUM_A009008
22 select SYS_FSL_ERRATUM_A009660
23 select SYS_FSL_ERRATUM_A009663
24 select SYS_FSL_ERRATUM_A009798
25 select SYS_FSL_ERRATUM_A009929
26 select SYS_FSL_ERRATUM_A009942
27 select SYS_FSL_ERRATUM_A010315
28 select SYS_FSL_ERRATUM_A010539
29 select SYS_FSL_HAS_DDR3
30 select SYS_FSL_HAS_DDR4
31 select ARCH_EARLY_INIT_R
32 select BOARD_EARLY_INIT_F
38 select ARMV8_SET_SMPEN
42 select SYS_FSL_DDR_VER_50
43 select SYS_FSL_ERRATUM_A008336
44 select SYS_FSL_ERRATUM_A008511
45 select SYS_FSL_ERRATUM_A008850
46 select SYS_FSL_ERRATUM_A008997
47 select SYS_FSL_ERRATUM_A009007
48 select SYS_FSL_ERRATUM_A009008
49 select SYS_FSL_ERRATUM_A009798
50 select SYS_FSL_ERRATUM_A009801
51 select SYS_FSL_ERRATUM_A009803
52 select SYS_FSL_ERRATUM_A009942
53 select SYS_FSL_ERRATUM_A010165
54 select SYS_FSL_ERRATUM_A010539
55 select SYS_FSL_HAS_DDR4
57 select ARCH_EARLY_INIT_R
58 select BOARD_EARLY_INIT_F
63 select ARMV8_SET_SMPEN
67 select SYS_FSL_DDR_VER_50
70 select SYS_FSL_ERRATUM_A009803
71 select SYS_FSL_ERRATUM_A009942
72 select SYS_FSL_ERRATUM_A010165
73 select SYS_FSL_ERRATUM_A008511
74 select SYS_FSL_ERRATUM_A008850
75 select SYS_FSL_ERRATUM_A009007
76 select SYS_FSL_HAS_CCI400
77 select SYS_FSL_HAS_DDR4
78 select SYS_FSL_HAS_RGMII
79 select SYS_FSL_HAS_SEC
80 select SYS_FSL_SEC_COMPAT_5
85 select ARCH_EARLY_INIT_R
86 select BOARD_EARLY_INIT_F
91 select ARMV8_SET_SMPEN
92 select ARM_ERRATA_826974
93 select ARM_ERRATA_828024
94 select ARM_ERRATA_829520
95 select ARM_ERRATA_833471
99 select SYS_FSL_DDR_VER_50
100 select SYS_FSL_HAS_CCN504
101 select SYS_FSL_HAS_DP_DDR
102 select SYS_FSL_HAS_SEC
103 select SYS_FSL_HAS_DDR4
104 select SYS_FSL_SEC_COMPAT_5
105 select SYS_FSL_SEC_LE
106 select SYS_FSL_SRDS_2
109 select SYS_FSL_ERRATUM_A008336
110 select SYS_FSL_ERRATUM_A008511
111 select SYS_FSL_ERRATUM_A008514
112 select SYS_FSL_ERRATUM_A008585
113 select SYS_FSL_ERRATUM_A008997
114 select SYS_FSL_ERRATUM_A009007
115 select SYS_FSL_ERRATUM_A009008
116 select SYS_FSL_ERRATUM_A009635
117 select SYS_FSL_ERRATUM_A009663
118 select SYS_FSL_ERRATUM_A009798
119 select SYS_FSL_ERRATUM_A009801
120 select SYS_FSL_ERRATUM_A009803
121 select SYS_FSL_ERRATUM_A009942
122 select SYS_FSL_ERRATUM_A010165
123 select SYS_FSL_ERRATUM_A009203
124 select ARCH_EARLY_INIT_R
125 select BOARD_EARLY_INIT_F
129 select SYS_FSL_HAS_CCI400
130 select SYS_FSL_HAS_SEC
131 select SYS_FSL_SEC_COMPAT_5
132 select SYS_FSL_SEC_BE
133 select SYS_FSL_SRDS_1
134 select SYS_HAS_SERDES
138 select SYS_FSL_SRDS_1
139 select SYS_HAS_SERDES
142 bool "Management Complex network"
143 depends on ARCH_LS2080A || ARCH_LS1088A
147 Enable Management Complex (MC) network
149 menu "Layerscape architecture"
150 depends on FSL_LSCH2 || FSL_LSCH3
152 config FSL_PCIE_COMPAT
153 string "PCIe compatible of Kernel DT"
154 depends on PCIE_LAYERSCAPE
155 default "fsl,ls1012a-pcie" if ARCH_LS1012A
156 default "fsl,ls1043a-pcie" if ARCH_LS1043A
157 default "fsl,ls1046a-pcie" if ARCH_LS1046A
158 default "fsl,ls2080a-pcie" if ARCH_LS2080A
159 default "fsl,ls1088a-pcie" if ARCH_LS1088A
161 This compatible is used to find pci controller node in Kernel DT
164 config HAS_FEATURE_GIC64K_ALIGN
166 default y if ARCH_LS1043A
168 config HAS_FEATURE_ENHANCED_MSI
170 default y if ARCH_LS1043A
172 menu "Layerscape PPA"
174 bool "FSL Layerscape PPA firmware support"
175 depends on !ARMV8_PSCI
176 select ARMV8_SEC_FIRMWARE_SUPPORT
177 select SEC_FIRMWARE_ARMV8_PSCI
178 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
180 The FSL Primary Protected Application (PPA) is a software component
181 which is loaded during boot stage, and then remains resident in RAM
182 and runs in the TrustZone after boot.
185 config SPL_FSL_LS_PPA
186 bool "FSL Layerscape PPA firmware support for SPL build"
187 depends on !ARMV8_PSCI
188 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
189 select SEC_FIRMWARE_ARMV8_PSCI
190 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
192 The FSL Primary Protected Application (PPA) is a software component
193 which is loaded during boot stage, and then remains resident in RAM
194 and runs in the TrustZone after boot. This is to load PPA during SPL
195 stage instead of the RAM version of U-Boot. Once PPA is initialized,
196 the rest of U-Boot (including RAM version) runs at EL2.
198 prompt "FSL Layerscape PPA firmware loading-media select"
199 depends on FSL_LS_PPA
200 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
201 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
202 default SYS_LS_PPA_FW_IN_XIP
204 config SYS_LS_PPA_FW_IN_XIP
207 Say Y here if the PPA firmware locate at XIP flash, such
208 as NOR or QSPI flash.
210 config SYS_LS_PPA_FW_IN_MMC
211 bool "eMMC or SD Card"
213 Say Y here if the PPA firmware locate at eMMC/SD card.
215 config SYS_LS_PPA_FW_IN_NAND
218 Say Y here if the PPA firmware locate at NAND flash.
222 config SYS_LS_PPA_FW_ADDR
223 hex "Address of PPA firmware loading from"
224 depends on FSL_LS_PPA
225 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
226 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
227 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
228 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
229 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
230 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
231 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
234 If the PPA firmware locate at XIP flash, such as NOR or
235 QSPI flash, this address is a directly memory-mapped.
236 If it is in a serial accessed flash, such as NAND and SD
237 card, it is a byte offset.
239 config SYS_LS_PPA_ESBC_ADDR
240 hex "hdr address of PPA firmware loading from"
241 depends on FSL_LS_PPA && CHAIN_OF_TRUST
242 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
243 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
244 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
245 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
246 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
247 default 0x680000 if SYS_LS_PPA_FW_IN_MMC
248 default 0x680000 if SYS_LS_PPA_FW_IN_NAND
250 If the PPA header firmware locate at XIP flash, such as NOR or
251 QSPI flash, this address is a directly memory-mapped.
252 If it is in a serial accessed flash, such as NAND and SD
253 card, it is a byte offset.
255 config LS_PPA_ESBC_HDR_SIZE
256 hex "Length of PPA ESBC header"
257 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
260 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
261 NAND to memory to validate PPA image.
265 config SYS_FSL_ERRATUM_A008997
266 bool "Workaround for USB PHY erratum A008997"
268 config SYS_FSL_ERRATUM_A009007
271 Workaround for USB PHY erratum A009007
273 config SYS_FSL_ERRATUM_A009008
274 bool "Workaround for USB PHY erratum A009008"
276 config SYS_FSL_ERRATUM_A009798
277 bool "Workaround for USB PHY erratum A009798"
279 config SYS_FSL_ERRATUM_A010315
280 bool "Workaround for PCIe erratum A010315"
282 config SYS_FSL_ERRATUM_A010539
283 bool "Workaround for PIN MUX erratum A010539"
286 int "Maximum number of CPUs permitted for Layerscape"
287 default 4 if ARCH_LS1043A
288 default 4 if ARCH_LS1046A
289 default 16 if ARCH_LS2080A
290 default 8 if ARCH_LS1088A
293 Set this number to the maximum number of possible CPUs in the SoC.
294 SoCs may have multiple clusters with each cluster may have multiple
295 ports. If some ports are reserved but higher ports are used for
296 cores, count the reserved ports. This will allocate enough memory
297 in spin table to properly handle all cores.
302 Enable Freescale Secure Boot feature
305 bool "Init the QSPI AHB bus"
307 The default setting for QSPI AHB bus just support 3bytes addressing.
308 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
309 bus for those flashes to support the full QSPI flash size.
311 config SYS_CCI400_OFFSET
312 hex "Offset for CCI400 base"
313 depends on SYS_FSL_HAS_CCI400
314 default 0x3090000 if ARCH_LS1088A
315 default 0x180000 if FSL_LSCH2
317 Offset for CCI400 base
318 CCI400 base addr = CCSRBAR + CCI400_OFFSET
320 config SYS_FSL_IFC_BANK_COUNT
321 int "Maximum banks of Integrated flash controller"
322 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
323 default 4 if ARCH_LS1043A
324 default 4 if ARCH_LS1046A
325 default 8 if ARCH_LS2080A || ARCH_LS1088A
327 config SYS_FSL_HAS_CCI400
330 config SYS_FSL_HAS_CCN504
333 config SYS_FSL_HAS_DP_DDR
336 config SYS_FSL_SRDS_1
339 config SYS_FSL_SRDS_2
342 config SYS_HAS_SERDES
353 menu "Layerscape clock tree configuration"
354 depends on FSL_LSCH2 || FSL_LSCH3
357 bool "Enable clock tree initialization"
360 config CLUSTER_CLK_FREQ
361 int "Reference clock of core cluster"
362 depends on ARCH_LS1012A
365 This number is the reference clock frequency of core PLL.
366 For most platforms, the core PLL and Platform PLL have the same
367 reference clock, but for some platforms, LS1012A for instance,
368 they are provided sepatately.
370 config SYS_FSL_PCLK_DIV
371 int "Platform clock divider"
372 default 1 if ARCH_LS1043A
373 default 1 if ARCH_LS1046A
374 default 1 if ARCH_LS1088A
377 This is the divider that is used to derive Platform clock from
378 Platform PLL, in another word:
379 Platform_clk = Platform_PLL_freq / this_divider
381 config SYS_FSL_DSPI_CLK_DIV
382 int "DSPI clock divider"
383 default 1 if ARCH_LS1043A
386 This is the divider that is used to derive DSPI clock from Platform
387 clock, in another word DSPI_clk = Platform_clk / this_divider.
389 config SYS_FSL_DUART_CLK_DIV
390 int "DUART clock divider"
391 default 1 if ARCH_LS1043A
394 This is the divider that is used to derive DUART clock from Platform
395 clock, in another word DUART_clk = Platform_clk / this_divider.
397 config SYS_FSL_I2C_CLK_DIV
398 int "I2C clock divider"
399 default 1 if ARCH_LS1043A
402 This is the divider that is used to derive I2C clock from Platform
403 clock, in another word I2C_clk = Platform_clk / this_divider.
405 config SYS_FSL_IFC_CLK_DIV
406 int "IFC clock divider"
407 default 1 if ARCH_LS1043A
410 This is the divider that is used to derive IFC clock from Platform
411 clock, in another word IFC_clk = Platform_clk / this_divider.
413 config SYS_FSL_LPUART_CLK_DIV
414 int "LPUART clock divider"
415 default 1 if ARCH_LS1043A
418 This is the divider that is used to derive LPUART clock from Platform
419 clock, in another word LPUART_clk = Platform_clk / this_divider.
421 config SYS_FSL_SDHC_CLK_DIV
422 int "SDHC clock divider"
423 default 1 if ARCH_LS1043A
424 default 1 if ARCH_LS1012A
427 This is the divider that is used to derive SDHC clock from Platform
428 clock, in another word SDHC_clk = Platform_clk / this_divider.
434 Reserve memory from the top, tracked by gd->arch.resv_ram. This
435 reserved RAM can be used by special driver that resides in memory
436 after U-Boot exits. It's up to implementation to allocate and allow
437 access to this reserved memory. For example, the reserved RAM can
438 be at the high end of physical memory. The reserve RAM may be
439 excluded from memory bank(s) passed to OS, or marked as reserved.
444 Ethernet controller 1, this is connected to MAC3.
445 Provides DPAA2 capabilities
450 Ethernet controller 2, this is connected to MAC4.
451 Provides DPAA2 capabilities
453 config SYS_FSL_ERRATUM_A008336
456 config SYS_FSL_ERRATUM_A008514
459 config SYS_FSL_ERRATUM_A008585
462 config SYS_FSL_ERRATUM_A008850
465 config SYS_FSL_ERRATUM_A009203
468 config SYS_FSL_ERRATUM_A009635
471 config SYS_FSL_ERRATUM_A009660
474 config SYS_FSL_ERRATUM_A009929
478 config SYS_FSL_HAS_RGMII
480 depends on SYS_FSL_EC1 || SYS_FSL_EC2
483 config SYS_MC_RSV_MEM_ALIGN
484 hex "Management Complex reserved memory alignment"
486 default 0x20000000 if ARCH_LS2080A
487 default 0x70000000 if ARCH_LS1088A
489 Reserved memory needs to be aligned for MC to use. Default value
493 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
495 config HAS_FSL_XHCI_USB
497 default y if ARCH_LS1043A || ARCH_LS1046A
499 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
500 pins, select it when the pins are assigned to USB.