6 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_DDR_VER_50
13 select SYS_FSL_ERRATUM_A010315
14 select SYS_FSL_ERRATUM_A010539
21 select SYS_FSL_DDR_VER_50
22 select SYS_FSL_ERRATUM_A010539
30 select SYS_FSL_DDR_VER_50
31 select SYS_FSL_HAS_DP_DDR
32 select SYS_FSL_HAS_SEC
33 select SYS_FSL_SEC_COMPAT_5
39 select SYS_FSL_HAS_SEC
40 select SYS_FSL_SEC_COMPAT_5
50 menu "Layerscape architecture"
51 depends on FSL_LSCH2 || FSL_LSCH3
55 bool "FSL Layerscape PPA firmware support"
56 depends on !ARMV8_PSCI
57 depends on ARCH_LS1043A || ARCH_LS1046A
58 select FSL_PPA_ARMV8_PSCI
60 The FSL Primary Protected Application (PPA) is a software component
61 which is loaded during boot stage, and then remains resident in RAM
62 and runs in the TrustZone after boot.
65 config FSL_PPA_ARMV8_PSCI
66 bool "PSCI implementation in PPA firmware"
69 This config enables the ARMv8 PSCI implementation in PPA firmware.
70 This is a private PSCI implementation and different from those
71 implemented under the common ARMv8 PSCI framework.
77 config SYS_FSL_ERRATUM_A010315
78 bool "Workaround for PCIe erratum A010315"
80 config SYS_FSL_ERRATUM_A010539
81 bool "Workaround for PIN MUX erratum A010539"
84 int "Maximum number of CPUs permitted for Layerscape"
85 default 4 if ARCH_LS1043A
86 default 4 if ARCH_LS1046A
87 default 16 if ARCH_LS2080A
90 Set this number to the maximum number of possible CPUs in the SoC.
91 SoCs may have multiple clusters with each cluster may have multiple
92 ports. If some ports are reserved but higher ports are used for
93 cores, count the reserved ports. This will allocate enough memory
94 in spin table to properly handle all cores.
96 config NUM_DDR_CONTROLLERS
97 int "Maximum DDR controllers"
98 default 3 if ARCH_LS2080A
104 Enable Freescale Secure Boot feature
107 bool "Init the QSPI AHB bus"
109 The default setting for QSPI AHB bus just support 3bytes addressing.
110 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
111 bus for those flashes to support the full QSPI flash size.
113 config SYS_FSL_IFC_BANK_COUNT
114 int "Maximum banks of Integrated flash controller"
115 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
116 default 4 if ARCH_LS1043A
117 default 4 if ARCH_LS1046A
118 default 8 if ARCH_LS2080A
120 config SYS_FSL_HAS_DP_DDR
123 config SYS_FSL_SRDS_1
126 config SYS_FSL_SRDS_2
129 config SYS_HAS_SERDES
133 bool "Freescale DDR driver"
135 Select Freescale General DDR driver, shared between most Freescale
136 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
137 based Layerscape SoCs (such as ls2080a).
139 config SYS_FSL_DDR_BE
142 Access DDR registers in big-endian.
144 config SYS_FSL_DDR_LE
147 Access DDR registers in little-endian.
149 config SYS_FSL_DDR_VER
151 default 50 if SYS_FSL_DDR_VER_50
153 config SYS_FSL_DDR_VER_50
156 config SYS_FSL_DDRC_ARM_GEN3
159 config SYS_FSL_DDRC_GEN4
163 bool "Freescale DDR3 controller"
164 depends on !SYS_FSL_DDR4
166 select SYS_FSL_DDRC_ARM_GEN3
168 Enable Freescale DDR3 controller on ARM-based SoCs.
171 bool "Freescale DDR4 controller"
173 select SYS_FSL_DDRC_GEN4
175 Enable Freescale DDR4 controller.