7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
32 select ARMV8_SET_SMPEN
36 select SYS_FSL_DDR_VER_50
37 select SYS_FSL_ERRATUM_A008336
38 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A009801
40 select SYS_FSL_ERRATUM_A009803
41 select SYS_FSL_ERRATUM_A009942
42 select SYS_FSL_ERRATUM_A010165
43 select SYS_FSL_ERRATUM_A010539
44 select SYS_FSL_HAS_DDR4
46 select ARCH_EARLY_INIT_R
47 select BOARD_EARLY_INIT_F
51 select ARMV8_SET_SMPEN
52 select ARM_ERRATA_826974
53 select ARM_ERRATA_828024
54 select ARM_ERRATA_829520
55 select ARM_ERRATA_833471
59 select SYS_FSL_DDR_VER_50
60 select SYS_FSL_HAS_DP_DDR
61 select SYS_FSL_HAS_SEC
62 select SYS_FSL_HAS_DDR4
63 select SYS_FSL_SEC_COMPAT_5
66 select SYS_FSL_ERRATUM_A008336
67 select SYS_FSL_ERRATUM_A008511
68 select SYS_FSL_ERRATUM_A008514
69 select SYS_FSL_ERRATUM_A008585
70 select SYS_FSL_ERRATUM_A009635
71 select SYS_FSL_ERRATUM_A009663
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803
74 select SYS_FSL_ERRATUM_A009942
75 select SYS_FSL_ERRATUM_A010165
76 select ARCH_EARLY_INIT_R
77 select BOARD_EARLY_INIT_F
81 select SYS_FSL_HAS_SEC
82 select SYS_FSL_SEC_COMPAT_5
93 bool "Management Complex network"
94 depends on ARCH_LS2080A
98 Enable Management Complex (MC) network
100 menu "Layerscape architecture"
101 depends on FSL_LSCH2 || FSL_LSCH3
103 config FSL_PCIE_COMPAT
104 string "PCIe compatible of Kernel DT"
105 depends on PCIE_LAYERSCAPE
106 default "fsl,ls1012a-pcie" if ARCH_LS1012A
107 default "fsl,ls1043a-pcie" if ARCH_LS1043A
108 default "fsl,ls1046a-pcie" if ARCH_LS1046A
109 default "fsl,ls2080a-pcie" if ARCH_LS2080A
111 This compatible is used to find pci controller node in Kernel DT
114 config HAS_FEATURE_GIC64K_ALIGN
116 default y if ARCH_LS1043A
118 config HAS_FEATURE_ENHANCED_MSI
120 default y if ARCH_LS1043A
122 menu "Layerscape PPA"
124 bool "FSL Layerscape PPA firmware support"
125 depends on !ARMV8_PSCI
126 select ARMV8_SEC_FIRMWARE_SUPPORT
127 select SEC_FIRMWARE_ARMV8_PSCI
128 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
130 The FSL Primary Protected Application (PPA) is a software component
131 which is loaded during boot stage, and then remains resident in RAM
132 and runs in the TrustZone after boot.
135 prompt "FSL Layerscape PPA firmware loading-media select"
136 depends on FSL_LS_PPA
137 default SYS_LS_PPA_FW_IN_XIP
139 config SYS_LS_PPA_FW_IN_XIP
142 Say Y here if the PPA firmware locate at XIP flash, such
143 as NOR or QSPI flash.
147 config SYS_LS_PPA_FW_ADDR
148 hex "Address of PPA firmware loading from"
149 depends on FSL_LS_PPA
150 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
151 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
153 If the PPA firmware locate at XIP flash, such as NOR or
154 QSPI flash, this address is a directly memory-mapped.
155 If it is in a serial accessed flash, such as NAND and SD
156 card, it is a byte offset.
159 config SYS_FSL_ERRATUM_A010315
160 bool "Workaround for PCIe erratum A010315"
162 config SYS_FSL_ERRATUM_A010539
163 bool "Workaround for PIN MUX erratum A010539"
166 int "Maximum number of CPUs permitted for Layerscape"
167 default 4 if ARCH_LS1043A
168 default 4 if ARCH_LS1046A
169 default 16 if ARCH_LS2080A
172 Set this number to the maximum number of possible CPUs in the SoC.
173 SoCs may have multiple clusters with each cluster may have multiple
174 ports. If some ports are reserved but higher ports are used for
175 cores, count the reserved ports. This will allocate enough memory
176 in spin table to properly handle all cores.
181 Enable Freescale Secure Boot feature
184 bool "Init the QSPI AHB bus"
186 The default setting for QSPI AHB bus just support 3bytes addressing.
187 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
188 bus for those flashes to support the full QSPI flash size.
190 config SYS_FSL_IFC_BANK_COUNT
191 int "Maximum banks of Integrated flash controller"
192 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
193 default 4 if ARCH_LS1043A
194 default 4 if ARCH_LS1046A
195 default 8 if ARCH_LS2080A
197 config SYS_FSL_HAS_DP_DDR
200 config SYS_FSL_SRDS_1
203 config SYS_FSL_SRDS_2
206 config SYS_HAS_SERDES
211 menu "Layerscape clock tree configuration"
212 depends on FSL_LSCH2 || FSL_LSCH3
215 bool "Enable clock tree initialization"
218 config CLUSTER_CLK_FREQ
219 int "Reference clock of core cluster"
220 depends on ARCH_LS1012A
223 This number is the reference clock frequency of core PLL.
224 For most platforms, the core PLL and Platform PLL have the same
225 reference clock, but for some platforms, LS1012A for instance,
226 they are provided sepatately.
228 config SYS_FSL_PCLK_DIV
229 int "Platform clock divider"
230 default 1 if ARCH_LS1043A
231 default 1 if ARCH_LS1046A
234 This is the divider that is used to derive Platform clock from
235 Platform PLL, in another word:
236 Platform_clk = Platform_PLL_freq / this_divider
238 config SYS_FSL_DSPI_CLK_DIV
239 int "DSPI clock divider"
240 default 1 if ARCH_LS1043A
243 This is the divider that is used to derive DSPI clock from Platform
244 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
246 config SYS_FSL_DUART_CLK_DIV
247 int "DUART clock divider"
248 default 1 if ARCH_LS1043A
251 This is the divider that is used to derive DUART clock from Platform
252 clock, in another word DUART_clk = Platform_clk / this_divider.
254 config SYS_FSL_I2C_CLK_DIV
255 int "I2C clock divider"
256 default 1 if ARCH_LS1043A
259 This is the divider that is used to derive I2C clock from Platform
260 clock, in another word I2C_clk = Platform_clk / this_divider.
262 config SYS_FSL_IFC_CLK_DIV
263 int "IFC clock divider"
264 default 1 if ARCH_LS1043A
267 This is the divider that is used to derive IFC clock from Platform
268 clock, in another word IFC_clk = Platform_clk / this_divider.
270 config SYS_FSL_LPUART_CLK_DIV
271 int "LPUART clock divider"
272 default 1 if ARCH_LS1043A
275 This is the divider that is used to derive LPUART clock from Platform
276 clock, in another word LPUART_clk = Platform_clk / this_divider.
278 config SYS_FSL_SDHC_CLK_DIV
279 int "SDHC clock divider"
280 default 1 if ARCH_LS1043A
281 default 1 if ARCH_LS1012A
284 This is the divider that is used to derive SDHC clock from Platform
285 clock, in another word SDHC_clk = Platform_clk / this_divider.
291 Reserve memory from the top, tracked by gd->arch.resv_ram. This
292 reserved RAM can be used by special driver that resides in memory
293 after U-Boot exits. It's up to implementation to allocate and allow
294 access to this reserved memory. For example, the reserved RAM can
295 be at the high end of physical memory. The reserve RAM may be
296 excluded from memory bank(s) passed to OS, or marked as reserved.
298 config SYS_FSL_ERRATUM_A008336
301 config SYS_FSL_ERRATUM_A008514
304 config SYS_FSL_ERRATUM_A008585
307 config SYS_FSL_ERRATUM_A008850
310 config SYS_FSL_ERRATUM_A009635
313 config SYS_FSL_ERRATUM_A009660
316 config SYS_FSL_ERRATUM_A009929
319 config SYS_MC_RSV_MEM_ALIGN
320 hex "Management Complex reserved memory alignment"
324 Reserved memory needs to be aligned for MC to use. Default value